TS-7400 V2 ADC

The i.MX28 CPU provides 4 channels of LRADC, 12bit, with an absolute accuracy of 1.3% pre-calibration; this accuracy can be improved to near 0.5% via individual unit calibration. The TS-7400-V2 is configured to support 0-3.3 V inputs. In order to read the channels that are connected, use the following command:

tshwctl --cpuadc

The command will return output similar to the following:

LRADC_ADC1_millivolts=12
LRADC_ADC2_millivolts=10
LRADC_ADC3_millivolts=10
LRADC_ADC4_millivolts=3240
LRADC_ADC6_millivolts=6072
HSADC_millivolts=0

The channels are the pin names themselves, and the value is the voltage represented in mV.

A single execution of `tshwctl --cpuadc` takes around 10 ms real time. Integrating the source in to your own application can surely increase this acquisition speed. The LRADC has a maximum sample cycle of 428 kHz, all selected channels are sampled simultaneously on the same clock and processed round-robin, with each channel generating an interrupt upon conversion completion.

For more information about the LRADC, refer to the CPU manual.

HSADC

The i.MX28 also offers a single HSADC channel. This high-speed ADC can sample up to 2 Msps with a 12-bit resolution and an absolute accuracy of 1.3% which can be improved via individual unit calibration. The HSADC programming and operation is slightly different than the LRADC and requires application of the ENGR116296 errata workaround (applied already to our stock 'tshwctl --cpuadc' interface) in order to function properly.