TS-7680 Syscon

From embeddedTS Manuals

All of the registers below are 8 bits wide and are accessed through the I2C interface. The FPGA is located at 7 bit address 0x28 on the linux device /dev/i2c-0. Accessing registers can either be done directly via tshwctl with the --peek and --poke options, using tshwctl options to abstract some of the access details away, or directly accessing and manipulating the linux I2C device. See the tshwctl sources for an example of how this is implemented


Offset GPIO # Bits Usage [Initial value/MUX]
0x0
192 7:2 FPGA_22 Crossbar [GPIO] (RW)
1 FPGA_22 value [0] (RW)
0 FPGA_22 output enable [0] (RW)
0x1
193 7:2 FPGA_23 Crossbar [GPIO] (RW)
1 FPGA_23 value [0] (RW)
0 FPGA_23 output enable [0] (RW)
0x2
194 7:2 FPGA_24 Crossbar [GPIO] (RW)
1 FPGA_24 value [0] (RW)
0 FPGA_24 output enable [0] (RW)
0x3
195 7:2 FPGA_25 Crossbar [GPIO] (RW)
1 FPGA_25 value [0] (RW)
0 FPGA_25 output enable [0] (RW)
0x4
196 7:2 FPGA_26 Crossbar [GPIO] (RW)
1 FPGA_26 value [0] (RW)
0 FPGA_26 output enable [0] (RW)
0x5
197 7:2 FPGA_27 Crossbar [GPIO] (RW)
1 FPGA_27 value [0] (RW)
0 FPGA_27 output enable [0] (RW)
0x6
198 7:2 FPGA_28 Crossbar [GPIO] (RW)
1 FPGA_28 value [0] (RW)
0 FPGA_28 output enable [0] (RW)
0x7
199 7:2 FPGA_29 Crossbar [GPIO] (RW)
1 FPGA_29 value [0] (RW)
0 FPGA_29 output enable [0] (RW)
0x8
200 7:2 FPGA_30 Crossbar [GPIO] (RW)
1 FPGA_30 value [0] (RW)
0 FPGA_30 output enable [0] (RW)
0x9
201 7:2 FPGA_31 Crossbar [GPIO] (RW)
1 FPGA_31 value [0] (RW)
0 FPGA_31 output enable [0] (RW)
0xA
202 7:2 FPGA_32 Crossbar [GPIO] (RW)
1 FPGA_32 value [0] (RW)
0 FPGA_32 output enable [0] (RW)
0xB
203 7:2 FPGA_33 Crossbar [GPIO] (RW)
1 FPGA_33 value [0] (RW)
0 FPGA_33 output enable [0] (RW)
0xC
204 7:2 FPGA_34 Crossbar [GPIO] (RW)
1 FPGA_34 value [0] (RW)
0 FPGA_34 output enable [0] (RW)
0xD
205 7:2 FPGA_35 Crossbar [GPIO] (RW)
1 FPGA_35 value [0] (RW)
0 FPGA_35 output enable [0] (RW)
0xE
N/A 7:4 Reserved
3 DIG_IN 5V (RO)
2 DIO_2_IN (RO)
1 DIO_1_IN (RO)
0 DIO_0_IN (RO)
0xF
207 7:2 Reserved
1 Enable LS_DIO_0 [0] (RW)
0 Reserved
0x10
208 7:2 Reserved
1 Enable LS_DIO_1 [0] (RW)
0 Reserved
0x11
209 7:2 Reserved
1 Enable LS_DIO_2 [0] (RW)
0 Reserved
0x12
210 7:2 Reserved
1 Enable Relay 1 [0] (RW)
0 Reserved
0x13
211 7:2 Reserved
1 Enable Relay 2 [0] (RW)
0 Reserved
0x14
N/A 7:2 DC TXD Crossbar [Unassigned] (RW)
1 DC TXD value [0] (RW)
0 Reserved
0x15
N/A 7:2 COM1 TXD Crossbar [UART1_TXD] (RW)
1 COM1 TXD value [0] (RW)
0 Reserved
0x16
N/A 7:2 COM2 TXD Crossbar [UART4_TXD] (RW)
1 COM2 TXD value [0] (RW)
0 Reserved
0x17
N/A 7:2 MODBUS TXD Crossbar [UART2_TXD] (RW)
1 MODBUS TXD value [0] (RW)
0 Reserved
0x18
N/A 7:2 MODBUS TXEN Crossbar [UART2_TXEN] (RW)
1 MODBUS TXEN value [0] (RW)
0 Reserved
0x19
N/A 7:2 RS-485 TXD Crossbar [UART3_TXD] (RW)
1 RS-485 TXD value [0] (RW)
0 Reserved
0x1A
N/A 7:2 RS-485 TXEN Crossbar [UART3_TXEN] (RW)
1 RS-485 TXEN value [0] (RW)
0 Reserved
0x1B
N/A 7:2 Bluetooth RXD Crossbar [UART0_TXD] (RW)
1 Bluetooth RXD value [0] (RW)
0 Reserved
0x1C
N/A 7:2 Bluetooth CTS Crossbar [UART0_RTS] (RW)
1 Bluetooth CTS value [0] (RW)
0 Reserved
0x1D
N/A 7:2 UART0 RXD Crossbar [BT_TXD] (RW)
1 UART0 RXD value [0] (RW)
0 Reserved
0x1E
N/A 7:2 UART0 CTS Crossbar [BT_RTS] (RW)
1 UART0 CTS value [0] (RW)
0 Reserved
0x1F
N/A 7:2 UART1 RXD Crossbar [COM1_RXD] (RW)
1 UART1 RXD value [0] (RW)
0 Reserved
0x20
N/A 7:2 UART2 RXD Crossbar [MODBUS_RXD] (RW)
1 UART2 RXD value [0] (RW)
0 Reserved
0x21
N/A 7:2 UART3 RXD Crossbar [RS_485_RXD] (RW)
1 UART3 RXD value [0] (RW)
0 Reserved
0x22
N/A 7:2 UART4 RXD Crossbar [COM2_RXD] (RW)
1 UART4 RXD value [0] (RW)
0 Reserved
0x23
227 7:2 Reserved
1 En.# pullup AD0 [1] (RW)
0 Reserved
0x24
228 7:2 Reserved
1 En.# pullup AD1 [1] (RW)
0 Reserved
0x25
229 7:2 Reserved
1 En.# pullup AD2 [1] (RW)
0 Reserved
0x26
230 7:2 Reserved
1 En.# pullup AD3 [1] (RW)
0 Reserved
0x27
231 7:2 Reserved
1 En. Current loop AD 0-1 [0] (RW)
0 Reserved
0x28
232 7:2 Reserved
1 En. Current loop AD 2-3 [0] (RW)
0 Reserved
0x29
233 7:2 Reserved
1 En. 5v on DC header [0] (RW)
0 Reserved
0x2A
N/A 7:3 Reserved
2 Disable SPI interface (en. UART2 & 3) [0] (RW)
1 Boot SPI select; 0: offbd, 1: onbd [0] (RW)
0 Override automatic Boot SPI select [0] (RW)
0x2B
235 7:2 Reserved
1 Ethernet reset# [0] (RW)
0 Reserved
0x2C
236 7:2 Reserved
1 WLAN En. [0] (RW)
0 Reserved
0x2D
237 7:2 Reserved
1 Bluetooth En. [0] (RW)
0 Reserved
0x2E
N/A 7:4 Unused
3:0 Bits 11:8 of DAC0 PWM value [0] (RW)[1]
0x2F N/A 7:0 Bits 7:0 of DAC0 PWM value [0] (RW)
0x30
N/A 7:4 Unused
3:0 Bits 11:8 of DAC1 PWM value [0] (RW)[1]
0x31 N/A 7:0 Bits 7:0 of DAC1 PWM value [0] (RW)
0x32
N/A 7:4 Unused
3:0 Bits 11:8 of DAC2 PWM value [0] (RW)[1]
0x33 N/A 7:0 Bits 7:0 of DAC02 PWM value [0] (RW)
0x34
N/A 7:4 Unused
3:0 Bits 11:8 of DAC3 PWM value [0] (RW)[1]
0x35 N/A 7:0 Bits 7:0 of DAC3 PWM value [0] (RW)
0x36 N/A 7:0 Bits 23:16 of auto-485 #0 counter #0 [0] (RW)[1][2]
0x37 N/A 7:0 Bits 15:8 of auto-485 #0 counter #0 [0] (RW)[1][2]
0x38 N/A 7:0 Bits 7:0 of auto-485 #0 counter #0 [0] (RW)[2]
0x39 N/A 7:0 Bits 23:16 of auto-485 #0 counter #1 [0] (RW)[1][3]
0x3A N/A 7:0 Bits 15:8 of auto-485 #0 counter #1 [0] (RW)[1][3]
0x3B N/A 7:0 Bits 7:0 of auto-485 #0 counter #1 [0] (RW)[3]
0x3C N/A 7:0 Bits 23:16 of auto-485 #1 counter #0 [0] (RW)[1][2]
0x3D N/A 7:0 Bits 15:8 of auto-485 #1 counter #0 [0] (RW)[1][2]
0x3E N/A 7:0 Bits 7:0 of auto-485 #1 counter #0 [0] (RW)[2]
0x3F N/A 7:0 Bits 23:16 of auto-485 #1 counter #1 [0] (RW)[1][3]
0x40 N/A 7:0 Bits 15:8 of auto-485 #1 counter #1 [0] (RW)[1][3]
0x41 N/A 7:0 Bits 7:0 of auto-485 #1 counter #1 [0] (RW)[3]
0x42 N/A 7:0 Bits 23:16 of auto-485 #2 counter #0 [0] (RW)[1][2]
0x43 N/A 7:0 Bits 15:8 of auto-485 #2 counter #0 [0] (RW)[1][2]
0x44 N/A 7:0 Bits 7:0 of auto-485 #2 counter #0 [0] (RW)[2]
0x45 N/A 7:0 Bits 23:16 of auto-485 #2 counter #1 [0] (RW)[1][3]
0x46 N/A 7:0 Bits 15:8 of auto-485 #2 counter #1 [0] (RW)[1][3]
0x47 N/A 7:0 Bits 7:0 of auto-485 #2 counter #1 [0] (RW)[3]
0x48 N/A 7:0 Bits 23:16 of auto-485 #3 counter #0 [0] (RW)[1][2]
0x49 N/A 7:0 Bits 15:8 of auto-485 #3 counter #0 [0] (RW)[1][2]
0x4A N/A 7:0 Bits 7:0 of auto-485 #3 counter #0 [0] (RW)[2]
0x4B N/A 7:0 Bits 23:16 of auto-485 #3 counter #1 [0] (RW)[1][3]
0x4C N/A 7:0 Bits 15:8 of auto-485 #3 counter #1 [0] (RW)[1][3]
0x4D N/A 7:0 Bits 7:0 of auto-485 #3 counter #1 [0] (RW)[3]
0x4E N/A 7:0 Bits 23:16 of auto-485 #4 counter #0 [0] (RW)[1][2]
0x4F N/A 7:0 Bits 15:8 of auto-485 #4 counter #0 [0] (RW)[1][2]
0x50 N/A 7:0 Bits 7:0 of auto-485 #4 counter #0 [0] (RW)[2]
0x51 N/A 7:0 Bits 23:16 of auto-485 #4 counter #1 [0] (RW)[1][3]
0x52 N/A 7:0 Bits 15:8 of auto-485 #4 counter #1 [0] (RW)[1][3]
0x53 N/A 7:0 Bits 7:0 of auto-485 #4 counter #1 [0] (RW)[3]
0x7E
NA 7:3 Reserved
2 WiFi Module present
1:0 Reserved
0x7F NA 7:0 FPGA Revision
  1. ↑ 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 MUST be written before bits 7:0
  2. ↑ 2.00 2.01 2.02 2.03 2.04 2.05 2.06 2.07 2.08 2.09 2.10 2.11 2.12 2.13 2.14 Value of counter #0 must be set to count to the mid-point of the stop bit based on a 25MHz clock
  3. ↑ 3.00 3.01 3.02 3.03 3.04 3.05 3.06 3.07 3.08 3.09 3.10 3.11 3.12 3.13 3.14 Value of counter #1 must be set to count to one-half bit time based on a 25MHz clock
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