TS-7840 FPGA
From embeddedTS Manuals
The TS-7840 includes an Intel Cyclone IV FPGA. This is connected to the CPU over a x1 PCIe 2.0 lane, and provides additional perihperals and IO expansion to the system.
The onboard FPGA also permits customization such as adding quadrature encoders, PWM, additional serial ports, DMX, or other unique communication protocols. Please contact Technologic Systems if you require custom FPGA logic.
The FPGA registers are in PCIe BAR0 of 1e6d:7840, and use legacy level based interrupts for the shared peripherals.
All FPGA peripherals have drivers in our default BSP, but the FPGA registers can be manually accessed with fpga_peekpoke:
# 0x0 maps to the FPGA syscon, and register 0 of the syscon returns the FPGA revision
fpga_peekpoke 32 0x0
This will return the revision, such as 0x23.
| Offset | Description |
|---|---|
| 0x0 | FPGA Syscon |
| 0x24 | FPGA DIO Bank 0 |
| 0x40 | FPGA DIO Bank 1 |
| 0x5c | FPGA DIO Bank 2 |
| 0xa4 | FPGA RNG |
| 0x100 | 16550 #0 (COM1 RS-232) |
| 0x108 | 16550 #1 (COM2 RS-232) |
| 0x110 | 16550 #2 (GPS) |
| 0x1118 | 16550 #3 (Nimbelink) |
| 0x120 | 16550 #4 (Iridium Modem) |
| 0x128 | 16550 #5 (DSL Modem Debug) |
| 0x130 | 16550 #6 (Mikrobus UART) |
| 0x138 | 16550 #7 (RS-485) |
| 0x140 | 16550 #8 (XBEE) |
| 0x200 | SJA1000 compatible CAN controller |
| 0x400 | SPI controller |
| 0x800 | SDcore |