TS-7970 DIO Table

From embeddedTS Manuals

The GPIO numbers in the table below are relevant to how the Linux references these numbers. The CPU documentation refers to bank and IO while Linux flattens this out to one number space.

Pins #224 and above are from the perspective of the FPGA rather than the CPU. For example, toggling the IO #224 is ttymxc2_rxd which does not toggle the cpu's uart pin, but the FPGA IO directed at that pin in the CPU. Many of these UART pins are not set as GPIO by default, and the FPGA includes its own crossbar. The UART pins will be mapped to cpu or fpga uarts.

Pad Name [1] GPIO Number Common Functions [2] Location
SD4_DAT3 43 USB HUB Reset# Onboard
DISP0_DAT23 145 SEL_DC_USB# Onboard
EIM_A16 54 EN_USB_5V Onboard
EIM_D27 91 Green LED Onboard
GPIO_2 2 Red LED Onboard
GPIO_9 9 Yellow LED Onboard
DISP0_DAT4 121 Blue LED Onboard
CSI0_DATA_EN 148 FPGA_IRQ_0 (FPGA UART irq) Onboard
GPIO_4 4 FPGA_IRQ_1 (unused) Onboard
DISP0_DAT20 142 Gyro IRQ Onboard
EIM_LBA 59 GPIO HD2 pin 3
EIM_OE 57 Modbus fault Onboard
EIM_RW 58 GPIO HD2 pin 22
EIM_A19 51 EN_MODBUS_24V# Onboard
DISP0_DAT5 122 EN_MODBUS_3V# Onboard
EIM_D23 87 EN_RTC_PWR Onboard
DISP0_DAT0 117 EN_CAN_1# Onboard
EIM_BCLK 191 EN_CAN_2# Onboard
DISP0_DAT7 124 GPIO HD1 pin 7
DISP0_DAT9 126 GPIO HD1 pin 21
DISP0_DAT10 127 GPIO HD1 pin 9
DISP0_DAT11 133 GPIO HD1 pin 14
EIM_CS0 55 GPIO HD2 pin 5
EIM_A24 132 GPIO HD2 pin 12
EIM_WAIT 128 GPIO HD2 pin 11
EIM_EB1 61 GPIO HD2 pin 10
EIM_DA0 64 GPIO HD2 pin 2
EIM_DA1 65 GPIO HD2 pin 4
EIM_DA2 66 GPIO HD2 pin 6
EIM_DA3 67 GPIO HD2 pin 8
EIM_DA4 68 GPIO HD2 pin 7
EIM_DA5 69 GPIO HD2 pin 9
EIM_DA6 70 GPIO HD2 pin 13
EIM_DA7 71 GPIO HD2 pin 15
EIM_DA8 72 GPIO HD2 pin 16
EIM_DA9 73 GPIO HD2 pin 17
EIM_DA10 74 GPIO HD2 pin 14
EIM_DA11 75 GPIO HD2 pin 24
EIM_DA12 76 GPIO HD2 pin 21
EIM_DA13 77 GPIO HD2 pin 19
EIM_DA14 78 GPIO HD2 pin 20
EIM_DA15 79 GPIO HD2 pin 18
  1. The pad name does not often correspond with the functionality of the IO we use, but can be used to reference the pad in the CPU manual.
  2. This does not contain all of the functions possible for a pin, but the common functions as they are used on our off the shelf basebords. Consult the i.MX6 CPU Reference manual, and FPGA crossbar section for a complete list.


The FPGA is used as a GPIO expander, and a crossbar. In most cases the FPGA IO are usable for low speed IO. The crossbar allows passing through some spare CPU GPIO which are interruptible.

Note: If any IO are used from the kernel, keep in mind these IO cannot be called from an interrupt context. These IO "can sleep". Instead of gpio_set_value use gpio_set_value_cansleep().

Some pins will need to be changed into GPIO before they can be used. For example, to toggle HD1 pin 12 (HD1_TXD):

tshwctl --dump
 root@ts-imx6:~# tshwctl --dump
   FPGA Pad    (DIR) (VAL) FPGA Output
   TTYMXC2_RXD ( in) (  0) HD1_RXD
   TTYMXC4_RXD ( in) (  0) STC_RXD
   TTYMXC2_CTS ( in) (  0) GPIO
   TTYMXC3_RXD ( in) (  0) RXD_232_COM
   TTYMXC1_CTS ( in) (  0) BT_RTS
   TTYMXC2_RTS ( in) (  1) GPIO
        MB_TXD ( in) (  0) TTYMAX1_TXD
  MB_TX_EN_485 ( in) (  0) TTYMAX1_TXEN
   STC_TXD_485 ( in) (  0) TTYMAX0_TXD
 STC_TX_EN_485 ( in) (  0) TTYMAX0_TXEN
   TXD_232_COM ( in) (  0) TTYMXC3_TXD
   RTS_232_COM ( in) (  0) TTYMAX2_TXD
       HD1_TXD ( in) (  0) TTYMXC2_TXD
        BT_CTS ( in) (  1) TTYMXC1_RTS

In this case HD1_TXD is the signal we want to toggle. The HD1_TXD signal is passing through TTYMXC2_TXD. It is possible to toggle ttymxc2_txd from the CPU as a GPIO, but the CPU IOMUXC would first need to be configured. On the CPU IOMUXC this is a UART, not a GPIO by default. On the FPGA as well this is configured to pass through the CPU pin, but it can be configured to be a GPIO:

export HD1_TXD=GPIO
tshwctl --set

Now running "tshwctl --dump" will show this HD1_TXD signal is now a GPIO. Refer to the below table to see the FPGA pin to toggle. In this case, 236.

echo 236 > /sys/class/gpio/export
echo high > /sys/class/gpio/gpio236/direction
echo low > /sys/class/gpio/gpio236/direction
Pad Name [1] GPIO Number Default Function Location
TTYMXC2_RXD 224 ttymxc2 rxd HD1 pin 12
TTYMXC4_RXD 225 ttymxc4 rxd P1-B pin 16
TTYMXC3_RXD 227 ttymxc3 rxd COM Header pin 2
TTYMXC1_CTS 228 ttymxc1 cts Onboard (Bluetooth RTS)
MB_TXD 230 ttyMAX1 txd Modbus RJ45 Data pins 4/5 +/-
MB_TX_EN_485 231 ttyMAX1 txen Onboard
STC_TXD_485 232 ttyMAX0 TXD P1-A Terminal Block pin 2, COM2 Header pin 1
STC_TX_EN_485 233 ttyMAX0 TXEN Onboard [2]
TXD_232_COM 234 ttymxc3 TXD COM2 Header pin 3
RTS_232_COM 235 ttyMAX2 TXD COM2 Header pin 7
HD1_TXD 236 ttymxc2 TXD HD1 pin 12
BT_EN 237 GPIO Onboard
WL_EN 238 GPIO Onboard
BT_RTS 239 ttymxc1 CTS Onboard
BT_CTS 240 ttymxc1 RTS Onboard
BT_RXD 241 ttymxc1 TXD Onboard
TTYMXC1_RXD 242 ttymxc1 TXD Onboard
HD1_DIO_1 243 GPIO HD1 pin 8
HD1_DIO_2 244 GPIO HD1 pin 6
HD1_DIO_3 245 GPIO HD1 pin 4
HD1_DIO_4 246 GPIO HD1 pin 2
HD1_DIO_5 247 GPIO HD1 pin 24
HD1_DIO_6 248 GPIO HD1 pin 22
EN_OUT_1 249 GPIO Onboard/Terminal Block P1-B pin 5
EN_OUT_2 250 GPIO Onboard/Terminal Block P1-B pin 6
STC_TXD_232 252 ttymxc4 TXD P1-B Terminal Block pin 7
FPGA Register 253 1 = Reboot on push_sw Register
FPGA Register 254 1 = Reboot Register
TTYMAX0_RXD 268 ttyMAX0 RXD P1-A Terminal Block pin 3, COM2 Header pin 6
TTYMAX1_RXD 269 ttyMAX1 RXD RJ45 2W-Modbus pin 5
TTYMAX2_RXD 270 ttyMAX2 RXD COM2 Header pin 8
HD1_SPI_CLK 282 #SPI, GPIO HD1 pin 17
HD1_SPI_MOSI 283 #SPI, GPIO HD1 pin 20
HD1_SPI_MISO 284 #SPI, GPIO HD1 pin 18
  1. The pad name rarely corresponds with the functionality of the IO we use. This name can be used to reference the pad in the CPU manual.
  2. This pin is set up to automatically toggle with TX data in the FPGA. You do not need to manually toggle this to transmit/receive.