TS-8820-4700
 | |
| Product Page | |
| Documentation | |
|---|---|
| Schematic | |
| Software Support | |
| TS-8820 source directory | |
| Dimensions (in enclosure) | |
| 6.35 inches (tall) by 7.714 inches (wide including DB9) by 1.14 inches (deep) |
Overview
The TS-8820-BOX is a rugged, feature-rich TS-SOCKET based baseboard and System-on-Module (SoM) combination for industrial applications. The TS-8820-BOX is powered by the TS-4100, TS-4700, TS-4710, TS-4720 or TS-4800 System-on-Module devices. The TS-8820-BOX enclosure exposes all of the available I/O on rugged screw terminals while protecting the SoM and other sensitive electronics. The TS-8820-BOX a tough, durable, flexible, powerful, and affordable industrial process control platform.
TS-4700
See the TS-4700 page for functionality regarding the CPU, FPGA, and OS.
|
Marvell PXA166 800MHz ARM9 |
Getting Started
- Place the TS-8820 base board on a firm non-conductive surface.
- Carefully, insert the TS-4000 Series System-onModule (SoM) by aligning and pressing evenly and firmly onto the pair of mating connectors
- Connect the console serial terminal cable
- Connect the Ethernet cable if applicable.
- Connect the GND and POWER screw terminals to a voltage source from 10V to 30V DC.
- Alternatively, the board can be powered through POE
- Apply power
- Monitor the TS-SOCKET SBC using a terminal emulator connected to the serial console port to verify that the board is operating properly
See the TS-4700 page for more details on dealing with the functionality of the SoM.
Getting Started with tsctl
Getting Started
First, download and install the latest version of tsctl as documented in the Getting Started Guide.
Now start the tsctl shell:
$ tsctl tsctl>
Let's check that we really have a TS-8820.
tsctl> System BaseBoardId 0x00008820
Digital Outputs
There are 6 digital outputs on the TS-8820: 4 isolated outputs (OUT1, OUT2, OUT3, and OUT4) on block P7, and two non-isolated outputs (OUT5, OUT6) on block P2. When libtsctl detects a TS-8820 present, it automatically defines mappings between these names and the corresponding DIO numbers. You can see the DIO numbers by calling the MapLookup function in the system object. First, let's switch to decimal output.
tsctl> Mode Dec tsctl> System MapLookup;8820_OUT1;8820_OUT2;8820_OUT3;8820_OUT4;8820_OUT5;8820_OUT6;;; 204 205 206 207 208 209
This output in these examples is using a TS-4700; if you are using a different CPU board (e.g. the TS-4800) the exact numbers will be different. The tsctl command line client automatically performs these lookups if you use the string name when a number is expected. Let's look at an example. There is an LED labelled LED9 on the TS-8820 which shows the current state of the OUT1 digital output. It is located between the P1 terminal block and the ethernet connector as shown in this picture:
First, let's check on the state of this LED. At power-up the DIO defaults to LOW, so unless something has changed that you should see the following output:
tsctl> DIO tsctl DIO> GetAsync 8820_OUT1 LOW
If the output is LOW, then run the following command to set it HIGH, then read back the value:
tsctl DIO> SetAsync 8820_OUT1 HIGH tsctl DIO> GetAsync 8820_OUT1 HIGH
Your board should now match the above picture, with LED9 on. You can experiment with OUT2 through OUT6. The isolated outputs correspond to LED 9 through LED12 while the non-isolated outputs each have two LEDs, one inverted and one non-inverted, these are LED13 and LED27, respectively, for OUT5, and LED14 and LED28, respectively, for OUT6. From the perspective of the above picture, the non-inverted LEDs (LED27 and LED28) are below the bottom of the picture, between terminal blocks P1 and P2.
Digital Inputs
There are 14 digital inputs on the TS-8820. The first 8 (named IN1 through IN8) are isolated, while the remaining 6 (named IN9 through IN 14) are only buffered To experiment with the digital inputs you will need to feed a compatible signal that can toggle the input under your control. The simplest way to do this will be to connect it to other outputs on the board. You will need several pieces of stripped wire long enough to connect various terminal points together. First, connect OUT1 to IN1. Since OUT1 is an isolated output it acts like a switch, so you will need to wire OUT1+ to a voltage reference and OUT1- to IN1+. Since IN is an isolated input, you will need to wire IN1- to a ground common with the reference voltage. The follow picture illustrates with the YELLOW wire connecting OUT1- to IN1+, the GRAY wire connecting IN1- to GROUND, and the RED wire connecting OUT1+ to EXT_12V_24V.
Now read the state of IN1. It should be INPUT_HIGH, as we set OUT1 to HIGH in the previous section. Next, set OUT1 to LOW and verify that IN1 follows to INPUT_LOW:
tsctl DIO> GetAsync 8820_IN1 INPUT_HIGH tsctl DIO> SetAsync 8820_OUT1 LOW tsctl DIO> GetAsync 8820_IN1 INPUT_LOW
ADC Channels
There are 16 ADC channels on the TS-8820. Continuing with our previously wired board, add a wire from OUT1+ to ADC11, as shown by the added GREEN wire in this picture:
Next, use the AIO Get command to read the analog value with OUT1 both in the LOW and HIGH states. Analog channels are zero-numbered in tsctl, so for ADC11 we read channel 10.
tsctl DIO> tsctl> AIO Get 10 1337 tsctl> DIO SetAsync OUT1 HIGH tsctl> AIO Get 10 39370
The readings you get will depend on the supply voltage you are using. The Get function returns a 32-bit value which is the raw reading of the ADC. The default range for the ADC is -10V to +10V, and the precision of the ADC is 16-bit. The voltage is calculated by the formula:
V=n*IV/2^p
where n is the value returned by the ADC, IV is the input voltage range (max input voltage - minimum input voltage) and p is the number of bits of precision.
V = 39370 * 20 / 2^16 = 12.014V
The low voltage is:
V = 1337 * 20 / 2^16 = 0.408V
Which corresponds to 0V. In this case, since the value is not quite zero, a calibration function might be desired.
In this example, we can see that we are using a 12V power supply.
DAC Channels
There are 4 DAC outputs. For this demonstration, first connect DAC1 to ADC1 as shown in the picture below.
The new BLUE wire makes the connection. The DAC outputs are 12-bit precision, so the output value will be in the range of 0-4095. The following commands will set DAC1 to 0V, 10V, and 5V, reading ADC1 after each change in output. Note that on the TS-8820 AIO instance 0 (the default) is the ADC, while the DAC is AIO instance 1.
tsctl> AIO:1 Put 0 0 1 tsctl> AIO Get 0 387 tsctl> AIO:1 Put 0 4095 1 tsctl> AIO Get 0 32767 tsctl> AIO:1 Put 0 2048 1 tsctl> AIO Get 0 16757
If you have a scope you may wish to experiment further. First, set up the scope to display 0-10V. Put a probe on OUT1, set the trigger for the channel the probe is on, and set the voltage level to trigger on a rising edge at a slightly positive voltage such as 0.5 V. Use a time division of 50ms. Set t=0 about one division from the left edge of the scope, and set up for a single capture. Then run the following commands:
SAMPLES=`I=0;while [ $I -le 4095 ]; do echo -n $I\;; let I=$I+1; done` tsctl "AIO:1 Put 0;$SAMPLES"
The first command creates a list of numbers from 0 to 4095, and the second sequentially feeds all the values to the DAC. If all goes well, you should see a ramp from 0V to 10V that takes under 300ms, or around 70us per sample output.
PWM
There are eight (8) PWM outputs available on the TS-8820. The first six override the digital outputs. From our previous section, OUT1 is already wired to ADC11. Let's change OUT1 to a PWM, and then take several ADC samples at different PWM frequencies to verify that it is working properly. First, let's set the parameters for the PWM using the EDIO class. This can be done using either the PWM function, which takes as parameters the low time and high time in nanoseconds, or the PWMfd function, which takes a frequency in milliHertz and a duty cycle in millionths of a percent. Let's use the first one to create a 500Hz square wave, that is, a 1 million nanosecond high time and a 1 million nanosecond low time.
tsctl> EDIO PWM 8820_OUT1 1000000 1000000 1
Next, before the PWM actually drives the output, we must set the OUT1 pin to MODE_PWM, as by default it is in MODE_DIO.
tsctl> Pin ModeSet 8820_OUT1 MODE_PWM 1
Now the PWM should be outputting a square wave. Let's take some A/D samples to confirm this. First, let's configure the sample period on the A/D channel in question. Since we have a 500Hz square wave, we will want our sample period to be no more than 1,000,000 nanoseconds (1 millisecond) long. However, just to be on the safe side we will sample ten times faster than this. The TS-8820 architecture divides the ADC into two banks of 8 channels each. If any channel in the top bank is enabled, then the corresponding channel in the lower bank must be enabled as well. This means we need to enable channel 2 needs to be enabled for channel 10 to be enabled.
Note: There are also simplified commands that can be used for configuration. Consult the API reference for these.
tsctl> AIO Configure -10:-10:-10:-10:-10:-10:-10:-10:-10:-10:-10:-10:-10:-10:-10:-10 10:10:10:10:10:10:10:10:10:10:10:10:10:10:10:10 16:16:16:16:16:16:16:16:16:16:16:16:16:16:16:16 0:0:100000:0:0:0:0:0:0:0:100000:0:0:0:0:0 0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0 0 1
Now let's take some samples. Since two channels are enabled, every other sample (starting with the second) will be channel 10.
tsctl> AIO Gets16 160 160 753:1605:753:1563:752:1533:752:1510:753:1492:753:1479:752:1468:752:1457:752:1448:753:1442: 753:1434:752:15215:753:15207:751:15204:753:15220:754:15224:752:15218:752:15208:752:15201:753:15220: 751:15222:752:15220:752:15208:751:15200:755:2610:752:1706:753:1618:753:1570:752:1537:753:1513: 752:1497:752:1482:754:1470:754:1459:752:1450:752:1443:752:1436:753:15205:751:15208:752:15204: 752:15214:753:15221:753:15220:752:15212:752:15202:753:15214:752:15223:753:15221:752:15210:752:15203: 752:4073:753:1739:753:1631:753:1577:752:1543:753:1518:753:1500:753:1486:752:1473:753:1461: 751:1452:752:1445:754:1438:753:15248:752:15211:752:15204:752:15210:752:15221:753:15224:753:15211: 753:15205:752:15210:753:15222:753:15222:753:15213:751:15205:751:13467:752:1778:753:1646:753:1588
The LOW value from the PWM is around 1500, and the HIGH value is around 15200. In the output above, we see around 13 samples LOW followed by 13 samples HIGH, except at the ends where we started or stopped sampling in the middle of a given state. We therefore have a 50% duty cycle, and we can calculate that the actual frequency of the PWM from this formula:
f = samples_per_second_base_unit / number_of_base_units / samples_per_cycle
1,000,000,000 / 100,000 / 26 = 384.615Hz
This is lower than our requested 500Hz, but why? The answer is that the TS-8200 PWM can only generate a fixed set of frequencies. When we request a given frequency, what we will actually get is the closest frequency that can be generated. The frequencies available are defined by 12207Hz/(2^prescalar), where the prescalar is 0-7. The available frequencies are therefore 12207Hz, 6104Hz, 3052Hz, 1526Hz, 763Hz, 381Hz, 190Hz, and 95Hz. 381Hz is 119Hz below 500Hz, while 763Hz is further away at 263Hz. Therefore, 381Hz was chosen.
H-Bridges
There are two H-bridges on the TS-8820. They are both driven as PWMs. The tsctl mappings associate "HB1" with the DIO for HB_OUT1 (with HB_OUT2 being the auxiliary pin), and "HB2" associates with the DIO for HB_OUT3 (with HB_OUT4 being the auxiliary pin). Therefore, controlling them is pretty much the same as controlling the other PWMs. The only exception is that an HBridge provides additional functionality of direction, since it consists of two outputs instead of one. There are four different states the H-Bridge can be in:
- HB_LEFT, in which the PWM drives a positive voltage on the primary pin associated with the H-Bridge with respect to the auxiliary pin.
- HB_RIGHT, in which the PWM drives a positive voltage on the secondary pin associated with the H-Bridge with respect to the primary pin.
- HB_FREE_RUNNING, in which no voltage in applied across either pin, effectively disconnecting them from the circuit
- HB_BRAKING in which both pins are connected to the same rail.
The TS-8820 does not support the HB_BRAKING state.
In the following example, we set the H-Bridge mode for H-Bridge 1 to HB_LEFT:
tsctl> EDIO HBridge 8820_HB1 HB_LEFT 1
Isolated CAN Port
There is an isolated CAN port which can be tested via the tsctl CAN commands.
Relays
There are four relays on the board. These are controlled as regular DIO. Note: There is a known issue in mappings for base boards which prevents the automatic association of names such as "RELAY1" with the correct DIO number. The issue is that such an association currently must be relative to the base board. However, the relays on the TS-8820 are driven by DIOs on the CPU board. We hope to fix this bug in the future. In the mean time it is necessary to use the connector names (or corresponding numbers) below: for RELAY1 use CN1_77 for RELAY2 use CN1_79 for RELAY3 use CN1_81 for RELAY4 use CN1_85
First, enter DIO SetAsync onto the command stack:
tsctl> DIO SetAsync
After each of the following outputs, a relay will click. The first four will be ON clicks, the last four will be OFF clicks.
tsctl DIO SetAsync> CN1_77 HIGH tsctl DIO SetAsync> CN1_79 HIGH tsctl DIO SetAsync> CN1_81 HIGH tsctl DIO SetAsync> CN1_85 HIGH tsctl DIO SetAsync> CN1_77 LOW tsctl DIO SetAsync> CN1_79 LOW tsctl DIO SetAsync> CN1_81 LOW tsctl DIO SetAsync> CN1_85 LOW
LEDS
There are 27 LEDs on the TS-8820. Of these LED5 through LED28 can be controlled as DIO through their respective names as LEDs. For example, the following command will turn off LED17 if it is not already on:
tsctl DIO SetAsync> LED17 LOW
However, if you have followed the steps in this guide from a board powered up with default software, you may notice that the LED was on but did not go off. This is because LED17 corresponds to digital output 1 (OUT1) which we previous set to PWM mode:
tsctl DIO SetAsync> tsctl DIO> tsctl> Pin ModeGet LED17 MODE_PWM tsctl> Pin ModeSet LED17 MODE_DIO
Now the LED should go off. Let's try to control LED9.
tsctl> DIO SetAsync LED9 HIGH tsctl> DIO GetAsync LED9 INPUT_LOW
LED9 corresponds to digital input 1, so we cannot drive it high.
Features
FPGA
The TS-8820 is powered by a Lattice XP2 FPGA with 5000 LUTs. Many but not all of the features listed in chapter 5 are driven by FPGA logic. The hardware functionality described in this document is programmed in the FPGA at the factory by default. The TS-SOCKET System-on-Module (SoM) also has an FPGA, but when an FPGA is mentioned in this document it should be assumed that the TS-8820 FPGA is being discussed.
The SoM communicates with the TS-8820 FPGA using the MUXBUS, a simple address/data bus defined by embeddedTS and implemented in the SoM FPGA. TS-8820 application developers do not need to understand the full hardware stack that enables TS-8820 registers to be accessed in memory space. It is necessary to program the MUXBUS registers with values that work for the TS-8820. See ts8820ctl source code for an example.
For applications that require custom logic or interfaces, contact embeddedTS regarding custom FPGA customization. Sources for the The TS-8820 FPGA are also available via special arrangement with embeddedTS, contact sales@embeddedTS.com for more information.
Non-Volatile RAM
The TS-8820 provides 2MB of battery backed static RAM. The RAM is accessed through a 4KB memory window. After programming the SRAM page register, 16 bit reads or writes can be performed to any part of the page.
This can be accessed through ts8820ctl:
echo "test" | ts8820ctl -W 5
ts8820ctl -R 5
| Note: | The SRAM is not populated by default. See U16 to verify the presence on your board. If you require battery backed SRAM please contact us. |
Battery Socket
The coin cell battery is not required for normal TS-8820 operation. The battery provides backup power for the battery backed SRAM and for the real time clock located on the SoM. Without a battery, however, a loss of power will result in a loss of RTC time in the SoM and SRAM data on the TS-8820.
Digital Outputs
The TS-8820 offers 6 digital outputs. OUT1 through OUT4 are isolated and act as a solid state relay capable of switching up to 40 VDC at 1 A continuous draw. OUT5 and OUT6 are non-isolated, able to sink up to 1 A continuous current, and are 40 VDC tolerant.
The outputs can be controlled directly through the 'ts8820ctl' application. See "ts8820ctl.c" and "ts8820.c" for examples of how this writes to the TS-8820 registers.
With the 'ts8820ctl' application, all 6 outputs are manipulated in a single command. That is, a 6-bit value is passed as an argument, and that value is directly set to the outputs. For example, to set OUT5:
ts8820ctl --setdio=0x10
When an output is activated its associated LED indicator is enabled to provide visual feedback.
Isolated Outputs
Digital outputs OUT1 through OUT4 are isolated, each having their own positive and negative terminal. Each isolated output acts as a solid state relay allowing current to flow through the contacts only when it is activated. The isolated outputs are able to switch up to 40 VDC at 1 A continuous current draw. Isolated output terminals are made available on the P7 terminal block.
Non-Isolated Outputs
Digital outputs OUT5 and OUT6 are non-isolated, they rely on the main TS-8820 ground and only have a single contact. Each non-isolated output is a low side switch capable of sinking current when activated. The non-isolated outputs are capable of sinking 1 A continuous current with 40 V input voltage. Non-isolated input terminals appear on the P2 terminal block.
PWM
The TS-8820 has 6 PWM outputs. PWM channels 1 to 6 feed digital outputs 1 to 6 respectively when the PWM override bit is set for a given output.
For all 8 PWM channels, the PWM frequency is approximately (12207/(2^prescaler)) Hz, where the prescaler value is 3 bits wide. That is, a prescaler value of 0 through 7. The PWM duty cycle has 12 bits of resolution. If bit 12 of a PWM register is set, then the PWM output for that channel will be 100% high. Otherwise, the duty cycle setting is divided by 4096 to give the effective duty cycle.
To give OUT5 a ~3 kHZ 50% duty cycle PWM output using ts8820ctl, the following arguments would be used:
# -P sets the PWM frequency via a prescaler value to (12207/(2^VALUE))Hz.
# --mvolts= sets the PWM duty cycle percentage from a decimal scale of 0-10000
# --pwm= PWM channel to enable and modify
ts8820ctl --pwm=5 --mvolts=5000 -P 2
Digital Inputs
The TS-8820 offers 14 digital input pins. There are 8 isolated inputs that are 30 V tolerant. The 6 non-isolated inputs are 40 V tolerant.
The inputs can be polled directly through the ts8820ctl application. See ts8820ctl.c and ts8820.c for examples of how this reads from the TS-8820 registers.
With the ts8820ctl application, all 14 inputs can be read with a single command. A 14-bit value is returned in hex in a format that can be parsed easily by scripting languages. For example, the following output indicates that IN1 and IN3 are active:
ts8820ctl --getdio
dio=0x5
When an input is activated its associated LED indicator is enabled to provide visual feedback.
Buffered Inputs
Digital inputs IN9 through IN14 are non-isolated, buffered, active low inputs. Each pin has a nominal threshold of 2.5 VDC, a 3.24 Kohm pull-up to 5 VDC, and are 40 VDC tolerant. Non-isolated inputs are located on the P2 terminal block.
Isolated Inputs
Digital inputs IN1 though IN8 are isolated, each having their own positive and negative terminal. In order to activate an input, a potential of at least 1.4 VDC and not more than 30 VDC must be generated across these terminals. Isolated input terminals are located on P1 and P7 terminal blocks.
ADC Channels
The TS-8820 offers 16 channels of single ended bi-polar ADC inputs. These ADC inputs are provided by two separate 8 channel ADC devices. Each ADC controller supports a selectable voltage (via GPIO from the SoM, see below) ranges of -5 V to +5 V as well as -10 V to +10 V. This means that each set of 8 channels can be set to different ranges. Each set of 8 channels are sampled simultaneously inside the ADC device.
All 16 ADC inputs are located on the P3, P4, and P5 terminal blocks. While each ADC has a pair of inputs, they are single ended ADC channels; all negative input terminals connect to the TS-8820 common ground.
Additionally, the ADC devices support a number of oversampling options, also controlled via GPIO from the SoM. Enabling oversampling has the effect of adding a digital filter function after the ADC. Increasing the oversampling ratio will decrease the effective sampling rate of the ADC but will increase the signal to noise ratio of each channel. The oversampling rate is shared between both ADC devices, that is, the rate can not be independently set per-device.
Setting the ADC voltage range:
| DIO | Val | Range |
|---|---|---|
| CN2_56 | 1 | -10 V to +10 V |
| CN2_56 | 0 | -5 V to +5 V |
| DIO | Val | Range |
|---|---|---|
| CN2_58 | 1 | -10 V to +10 V |
| CN2_58 | 0 | -5 V to +5 V |
Setting the oversampling rate:
| CN2_64 | CN2_62 | CN2_60 | OS Rate |
|---|---|---|---|
| 0 | 0 | 0 | N/A |
| 0 | 0 | 1 | 2 |
| 0 | 1 | 0 | 4 |
| 0 | 1 | 1 | 8 |
| 1 | 0 | 0 | 16 |
| 1 | 0 | 1 | 32 |
| 1 | 1 | 0 | 64 |
| 1 | 1 | 1 | Invalid |
| Note: | SoM GPIO pins will usually start as inputs with pull up resistors. Therefore the default range will likely be -10 V to +10 V with an invalid oversampling rate. It is advised to set up these pins before acquiring ADC samples. |
Current Loops (4-20 mA measurement)
All 16 ADC channels independently support 4-20 mA current loop measurements. This is achieved by setting a pin jumper for the respective channel on the current loop enable pin header. Setting a jumper will electrically enable a 220 Ω 0.5% resistor from the ADC channel to ground allowing for a constant current measurement.
Thermistor
The TS-8820 supports up to 8 thermistors on channels 1 though 8. Support for a thermistor is enabled via software, the ADC pullup bit of TS-8820 FPGA register 0x2. Setting bit 8 enables a pull up on ADC channels 1 and 2, setting bit 9 enables a pull up on ADC channels 3 and 4, and setting bit 10 enables a pull up on channels 5 through 8. When enabled, each channel will get a separate 6.04 kΩ resistor to +12.5 V allowing the use of a thermistor probe.
ADC Usage
The 'ts8820ctl' application can be used to quickly sample the ADCs. This will send simultaneous sampling commands to each of the two ADC devices which will then sample all 16 channels in total the amount of times specified. See the "ts8820ctl.c" and "ts8820.c" files for examples on how this operation takes place.
For example, to sample all of the channels 5 times, the following command would be used:
ts8820ctl --sample=5
Collected 80 samples total.
Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Ch 9 Ch10 Ch11 Ch12 Ch13 Ch14 Ch15 Ch16
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
-7626 2195 2193 2199 2192 2195 2195 2192 2189 2189 2193 2190 2189 2192 2191 2191
-7626 2194 2192 2198 2191 2194 2194 2191 2188 2189 2192 2189 2188 2191 2189 2190
-7626 2193 2191 2197 2190 2193 2193 2190 2187 2188 2191 2188 2186 2190 2189 2189
-7626 2189 2188 2193 2186 2189 2190 2186 2183 2184 2187 2184 2183 2186 2185 2185
-7626 2189 2187 2192 2186 2188 2189 2186 2183 2183 2187 2184 2182 2185 2184 2185
Above, channel 1 has a -7.62 V voltage source attached to it, all other channels are left unconnected. The range is set at -10 V to +10 V, and the oversampling rate is set to 64.
DAC Channels
The TS-8820 has 4 channels of 0 to +10 V DAC outputs. Each DAC channel has a positive and negative terminal connection. The negative side of the terminals are connected to the common ground of the TS-8820 and are non-isolated. The DAC terminals are on the P3 and P9 terminal blocks.
The DAC channels each have 12 bits of resolution that correspond to 0 to +10 V output. The upper bit (bit 15) of each register is a control bit that is used to synchronize the output of all 4 DAC channels. This means that all four registers can be updated without modifying the actual DAC output. Setting the control bit of any DAC channel register will case an update of the DAC output of all four channels. If the DAC register has not been modified, the update will still be sent but the actual output will remain the same. Reading this control bit will indicate if the synchronization is complete. Writing the DAC registers while the control bit is still asserted, indicating busy, will result in undefined behavior. The update process from setting the control bit to its completion takes approximately 3 microseconds.
When 0 is written to the control bit, the DAC values are updated internally in the FPGA but not transferred to the DAC. Thus any set of channels can be updated simultaneously by only writing a one on the final write.
The DAC channels can be controlled through 'ts8820ctl'. Note that the "--setdac" option to 'ts8820ctl' will always set the control bit of the selected register. See "ts8820ctl.c" and "ts8820.c" for an example of how this process works.
The following command would set DAC output 1 to 0.5 V:
ts8820ctl --setdac=1 --mvolts=500
H-Bridges
The TS-8820 supports 2 H-bridges on terminal block P6. One bridge drives terminals 1 and 2, and the second drives terminals 3 and 4. Each pair of terminals can be connected directly to a DC motor. Each H-bridge can supply up to 2.8A of current. See the PWM section for more information on how the H-bridges are driven.
Isolated CAN Port
The TS-8820 provides an isolated CAN port on the P10 terminal block. The CAN interface itself is from the SoM with the TS-8820 facilitating the isolated physical interface.
Optionally, a 124 ohm termination resistor can be electrically added by setting the Term. CAN jumper. You can find more details about CAN on the TS-4700 here.
Isolated RS-232
An isolated RS-232 port is on P10, with TX on terminal 7 and RX on terminal 8. The RS-232 port is driven by XUART1.
Isolated RS-485
An isolated RS-485 port is on P10. Terminals 5 and 6 are the + and - lines, respectively. The RS-485 port is driven by XUART0.
Relays
Terminal block P8 is connected to 4 SPDT relays. Each relay has a COM line which is always connected to either the NC line (relay not activated) or the NO line (relay activated). The 4 relays are controlled by the following DIO.
| Relay | DIO |
|---|---|
| 1 | DIO_8 |
| 2 | DIO_7 |
| 3 | DIO_6 |
| 4 | DIO_4 |
These are not toggled through the TS-8820 FPGA, or through ts8820ctl. You can control these using tsctl or by using the setdiopin function. For example:
# This only needs to be run if you are in debian
source /initrd/ts4700.subr
# Enable each relay
setdiopin 8 1
setdiopin 7 1
setdiopin 6 1
setdiopin 4 1
Power Supply
The TS-8820 can be powered via PoE or direct DC voltage input to the terminal block connectors. If PoE is not used, power must be supplied on terminal block P6.
DC via Terminal Blocks
Direct power input can be applied to the P6 terminal block. There are three terminals for power and three for a ground connection. Each of the three sets of terminals are electrically connected together internally in the TS-8820. Operational range of the TS-8820 is +10 VDC to +30 VDC on these inputs. Supply an external ground on terminal 10, 11, and/or 12. Supply +10 V to +30 V on terminal 7, 8, and/or 9.
802.3af PoE
The TS-8820 is IEEE 802.3af PoE compliant. This allows the whole unit to be powered directly from a PoE sourcing device.
When powered via PoE, +24 VDC is made available on the P6 terminal block power terminals. Ensure that the total power draw of the system does not exceed the limits defined by IEEE 802.3af and that power is not also supplied to the TS-8820 on these pins!
LEDS
The TS-8820 has 27 LEDs used to indicate the electrical status of the inputs and outputs on the device. LEDs are labelled as "LED#" on the PCB silkscreen.
The majority of the LEDs are not able to be directly controlled, they turn on or off as a reaction to the status of the I/O they are connected to. For example, when DIG_OUT1 is set, LED17 will turn on. The "System" LEDs are the exception to this and are controlled via the SoM LED interface.
| LED | FUNCTION | --- | LED | FUNCTION |
|---|---|---|---|---|
| 1 | System RED_LED | 2 | Doesn't exist. | |
| 3 | System Power | 4 | System GREEN_LED | |
| 5 | RELAY_1 | 6 | RELAY_2 | |
| 7 | RELAY_3 | 8 | RELAY_4 | |
| 9 | DIG_IN1 | 10 | DIG_IN2 | |
| 11 | DIG_IN3 | 12 | DIG_IN4 | |
| 13 | DIG_IN5 | 14 | DIG_IN6 | |
| 15 | DIG_IN7 | 16 | DIG_IN8 | |
| 17 | DIG_OUT1 | 18 | DIG_OUT2 | |
| 19 | DIG_OUT3 | 20 | DIG_OUT4 | |
| 21 | DIG_IN9 | 22 | DIG_IN10 | |
| 23 | DIG_IN11 | 24 | DIG_IN12 | |
| 25 | DIG_IN13 | 26 | DIG_IN14 | |
| 27 | DIG_OUT5 | 28 | DIG_OUT6 |
External Interfaces
Terminal Blocks
| Note: | Rev A TS-8820 PCBs have incorrect P1-P10 silkscreens. Use the diagram below. |
|
|
|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
|
|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
|
Ethernet Connector
The TS-8820 can connect to any Ethernet LAN. Ethernet is fully supported by any TS-SOCKET SoM. The Ethernet connector includes LEDs indicating link and activity. The link LED should be on whenever the TS-8820 is powered and connected to a LAN. This connector allows the TS-8820 to be powered by PoE.
USB Host
The USB is available on two ports as a USB 2.0 host.
 |
|
DB9 Connector
|
|
Register Map
Most of the access to the I/O is abstracted by 'ts8820ctl' and "ts8820.c", but it is also possible to access them directly through MUXBUS registers if applicable.
| Offset | Bits | Description |
|---|---|---|
| 0x0 | 15:0 | Model ID: Reads 0x8820 |
| 0x2 | 15:11 | Reserved |
| 10 | Pull-up 5-8 enable | |
| 9 | Pull-up 3-4 enable | |
| 8 | Pull-up 1-2 enable | |
| 7 | H-bridge 2 enable (contacts go high-Z otherwise) | |
| 6 | H-bridge 1 enable (contacts go high-Z otherwise) | |
| 5 | H-bridge 2 direction | |
| 4 | H-bridge 1 direction | |
| 3:0 | FPGA Revision | |
| 0x4 | 15:14 | Reserved |
| 13:0 | Digital inputs 14:1 | |
| 0x6 | 15:10 | Reserved |
| 9:0 | SRAM Page register | |
| 0x8 | 15:12 | Reserved |
| 11:6 | Override Digital Outputs 6:1 with PWM | |
| 5:0 | Digital Output Values 6:1 | |
| 0xa | 15:0 | Reserved |
| 0xc | 15:0 | Reserved |
| 0xe | 15:0 | Reserved |
| 0x10 | 15:13 | PWM #1 Prescaler |
| 12:0 | PWM #1 Duty Cycle | |
| 0x12 | 15:13 | PWM #2 Prescalar |
| 12:0 | PWM #2 Duty Cycle | |
| 0x14 | 15:13 | PWM #3 Prescaler |
| 12:0 | PWM #3 Duty Cycle | |
| 0x16 | 15:13 | PWM #4 Prescaler |
| 12:0 | PWM #4 Duty Cycle | |
| 0x18 | 15:13 | PWM #5 Prescaler |
| 12:0 | PWM #5 Duty Cycle | |
| 0x1a | 15:13 | PWM #6 Prescaler |
| 12:0 | PWM #6 Duty Cycle | |
| 0x1c | 15:13 | PWM #7 Prescaler (H Bridge 1) |
| 12:0 | PWM #7 Duty Cycle (H Bridge 1) | |
| 0x1e | 15:13 | PWM #8 Prescaler (H Bridge 2) |
| 12:0 | PWM #8 Duty Cycle (H Bridge 2) | |
| 0x20 | 15:0 | Pulse Counter #1 (RO) |
| 0x22 | 15:0 | Pulse Counter #2 (RO) |
| 0x24 | 15:0 | Pulse Counter #3 (RO) |
| 0x26 | 15:0 | Pulse Counter #4 (RO) |
| 0x28 | 15:0 | Pulse Counter #5 (RO) |
| 0x2a | 15:0 | Pulse Counter #6 (RO) |
| 0x2c | 15:0 | Pulse Counter #7 (RO) |
| 0x2e | 15:0 | Pulse Counter #8 (RO) |
| 0x30 | 15:0 | Pulse Counter #9 (RO) |
| 0x32 | 15:0 | Pulse Counter #10 (RO) |
| 0x34 | 15:0 | Pulse Counter #11 (RO) |
| 0x36 | 15:0 | Pulse Counter #12 (RO) |
| 0x38 | 15:0 | Pulse Counter #13 (RO) |
| 0x3a | 15:0 | Pulse Counter #14 (RO) |
| 0x3c | 15:0 | Reserved |
| 0x3e | 15:0 | Reserved |
| 0x80 | 15:0 | ADC Core ID (reads 0xadc1) |
| 0x82 | 15:8 | ADC Channel Mask (0 = do not save channel data) |
| 7:6 | Highest number chip to use (0-3, if 01 then sample chip 0 and chip 1) | |
| 5 | 1 = Force standby | |
| 4 | 1 = Use standby between samples to save power | |
| 3 | 1 = Smart DMA IRQ mode | |
| 2 | 1 = Enable IRQ | |
| 1 | 1 = Collect samples, 0 = stop | |
| 0 | 1 = Reset ADC chips and all FIFOs | |
| 0x84 | 15 | 1 = There has been a FIFO overflow since last reset |
| 14:0 | Number of samples available to be read | |
| 0x86 | 15:0 | Sample Data (RO) |
| 0x88 | 15:0 | Sampling period LSB (RW) |
| 0x8a | 15:0 | Sampling period MSB (RW) |
| 0x8c | 15:0 | IRQ Threshold (RW) |
| 0x8e | 15:0 | Reserved |
| 0x90 | 15:0 | Reserved |
| 0x92 | 15:0 | Reserved |
| 0x94 | 15:0 | Reserved |
| 0x96 | 15:0 | Reserved |
| 0x98 | 15:0 | Reserved |
| 0x9a | 15:0 | Reserved |
| 0x9c | 15:0 | Reserved |
| 0x9e | 15:0 | Reserved |
| 0xa0 | 15:0 | DAC 1 Control Register |
| 0xa2 | 15:0 | DAC 2 Control Register |
| 0xa4 | 15:0 | DAC 3 Control Register |
| 0xa6 | 15:0 | DAC 4 Control Register |
Product Notes
FCC Advisory
This equipment generates, uses, and can radiate radio frequency energy and if not installed and used properly (that is, in strict accordance with the manufacturer's instructions), may cause interference to radio and television reception. It has been type tested and found to comply with the limits for a Class A digital device in accordance with the specifications in Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment. Operation of this equipment in a residential area is likely to cause interference, in which case the owner will be required to correct the interference at his own expense.
If this equipment does cause interference, which can be determined by turning the unit on and off, the user is encouraged to try the following measures to correct the interference:
Reorient the receiving antenna. Relocate the unit with respect to the receiver. Plug the unit into a different outlet so that the unit and receiver are on different branch circuits. Ensure that mounting screws and connector attachment screws are tightly secured. Ensure that good quality, shielded, and grounded cables are used for all data communications. If necessary, the user should consult the dealer or an experienced radio/television technician for additional suggestions. The following booklets prepared by the Federal Communications Commission (FCC) may also prove helpful:
How to Identify and Resolve Radio-TV Interference Problems (Stock No. 004-000-000345-4) Interface Handbook (Stock No. 004-000-004505-7) These booklets may be purchased from the Superintendent of Documents, U.S. Government Printing Office, Washington, DC 20402.
Limited Warranty
See our Terms and Conditions for more details.