TS-9370
| WARNING: | This product is still in development. This means the documentation and product itself will change several times before the product is deemed ready for Engineering Sampling. Please force-refresh (shift-f5 or ⌘-shift-R on most browsers) to clear your cache when visiting this page to ensure you are viewing the most recent version of this documentation. Of course also please check back often as this information is subject to change. |
 | |
| Product Page | |
| Documentation | |
|---|---|
| Schematic | |
| FTP Path | |
| Processor | |
| NXP i.MX9352 | |
| 1.7 GHz Arm® Cortex®-A55/M33 | |
| i.MX93 Product Page | |
| CPU Documentation |
Overview
Getting Started
TS-9370 Models
U-Boot
Debian
Debian 12 - Bookworm
Ubuntu
Buildroot
Backup / Restore
Features
ADCs
The ADCs on the TS-9370 are supplied primarily via the FPGA. The i.MX93 at present (?) supplies only on-die temperature sensors. The SMC's ADCs supply dedicated voltage monitoring functions, and it also supplies an additional on-die temperature sensor that is physically isolated from the main CPU.
Audio Codec
Battery-backed RTC
Bluetooth
CAN
CPU
DisplayPort
eMMC Interface
Ethernet Ports (1000BaseT)
FPGA
FPGA Registers
The TS-9370's FPGA is connected to the CPU over the FlexSPI bus. This provides 32-bit access to the FPGA, mapped at 0x2800_0000.
For example, to read the FPGA's model/rev/info block:
root@tsimx9:~# memtool md -l 0x28000000+0x40
28000000: 00009370 00000104 a5b2da72 32fce7d1 p.......r......2
28000010: 00000000 00000000 00000000 00000000 ................
28000020: 00000000 00000000 00000000 00000000 ................
28000030: 00000000 00000000 00000000 00000000 ................
root@tsimx9:~#
| Offset | Description |
|---|---|
| 0x0000 | Model/Rev Info |
| 0x0040 | FPGA GPIO block #0 |
| 0x0080 | FPGA GPIO block #1 |
| 0x00C0 | FPGA GPIO block #2 |
FPGA GPIO Instances
| Note: | Unlike GPIO into the CPU, at present the FPGA GPIOs do not support interrupts. |
Each of the three GPIO blocks can manage up to 32 IO lines. The 32-bit registers controlling each block are defined as follows:
| Offset | Read Function | Write Function |
|---|---|---|
| 0x00 | Output Enables | Set OE Bits |
| 0x04 | Reserved | Clear OE Bits |
| 0x08 | Output Data | Set Data Bits |
| 0x0c | Input Data | Clear Data Bits |
| 0x10 | Reserved | Reserved |
| 0x14 | Reserved | Reserved |
| 0x18 | Reserved | Reserved |
| 0x1c | Reserved | Reserved |
GPIO
| Note: | This section is incomplete at this time. |
The i.MX93 CPU and FPGA GPIOs are exposed using a kernel character device. This interface provides a set of files and directories for interacting with GPIO which can be used from any language that interact with special files in linux using ioctl() or similar. For our platforms, we pre-install the "libgpiod" library and binaries. Documentation on these tools can be found here. This section only covers using these userspace tools and does not provide guidance on using the libgpiod library in end applications. Please see the libgpiod documentation for this purpose.
A user with suitable permissions to read and write /dev/gpiochip* files can immediately interact with GPIO pins. For example, to see if input power has failed:
gpioget $(gpiofind POWER_FAIL_3V)
Multiple pins in the same chip can be read simultaneously by passing multiple pin numbers separated by spaces.
To write to a pin, the gpioset command is used. For example, to set Relay 1:
gpioset $(gpiofind EN_RELAY_1)=1
Multiple pins in the same chip can be set simultaneously by passing multiple pin=value pairs separated by spaces.
If a call with gpioset or gpioget fails with "Device or resource busy," that means that specific GPIO is claimed by another device. The command cat /sys/kernel/debug/gpio can be used to get a list of all of the system GPIO and what has claimed them.
The gpiomon tool can be used to monitor pins for changes to GPIOs that generate interrupts (i.e., CPU GPIOs).
In the following table, gpiochips 0, 3 and 4 are on the CPU, and gpiochips 5 through 7 are on the FPGA.
Because this numbering is subject to change, it is advisable to use the gpiofind command to look it up by its label, as shown in the usage examples above and elsewhere in this manual.
| Schematic Net Name | Chip | Bank | Line | Location |
|---|---|---|---|---|
EN_GREEN_LED_N
|
FPGA | 0 | 0 | |
EN_YEL_LED_N
|
FPGA | 0 | 1 | |
EN_RED_LED_N
|
FPGA | 0 | 2 | |
NIM_RESET_N
|
FPGA | 0 | 4 | |
NIM_CTS_N
|
FPGA | 0 | 5 | |
NIM_PWR_ON_N
|
FPGA | 0 | 6 | |
EN_NIM_USB_N
|
FPGA | 0 | 7 | |
EN_NIM_4V
|
FPGA | 0 | 8 | |
EN_NIM_3P3V
|
FPGA | 0 | 9 | |
NIM_TXD
|
FPGA | 0 | 10 | |
NIM_RXD
|
FPGA | 0 | 11 | |
EN_USB_HOST1_VBUS
|
FPGA | 0 | 12 | |
EN_USB_HOST2_VBUS
|
FPGA | 0 | 13 | |
MIKRO_TXD
|
FPGA | 0 | 14 | |
MIKRO_RXD
|
FPGA | 0 | 15 | |
MIKRO_SPI_CLK
|
FPGA | 0 | 16 | |
MIKRO_SPI_CS_N
|
FPGA | 0 | 17 | |
MIKRO_SPI_MISO
|
FPGA | 0 | 18 | |
MIKRO_SPI_MOSI
|
FPGA | 0 | 19 | |
MIKRO_RESET_N
|
FPGA | 0 | 20 | |
MIKRO_AN
|
FPGA | 0 | 21 | |
MIKRO_PWM
|
FPGA | 0 | 22 | |
MIKRO_INT
|
FPGA | 0 | 23 | |
EN_LS_OUT_1
|
FPGA | 0 | 24 | |
EN_LS_OUT_2
|
FPGA | 0 | 25 | |
EN_LS_OUT_3
|
FPGA | 0 | 26 | |
EN_LS_OUT_4
|
FPGA | 0 | 27 | |
EN_HS_SW
|
FPGA | 0 | 28 | |
DIO_FAULT_N
|
FPGA | 0 | 29 | |
MAGNET_IRQ[1]
|
FPGA | 0 | 30 | |
GYRO_IRQ[1]
|
FPGA | 0 | 31 | |
PUSH_SW_PADN
|
FPGA | 1 | 22 | |
AN_SEL_0
|
FPGA | 1 | 23 | |
AN_SEL_1
|
FPGA | 1 | 24 | |
EN_CL_1_2
|
FPGA | 1 | 25 | |
EN_CL_3
|
FPGA | 1 | 26 | |
DP_RESET_PADN
|
FPGA | 1 | 27 | |
NO_SCAP_CHRG_PADN
|
FPGA | 1 | 28 | |
EN_SPKR_AMP
|
FPGA | 1 | 29 | |
BT_EN
|
FPGA | 1 | 30 | |
WIFI_EN
|
FPGA | 1 | 31 | |
EN_ADC_3_12V
|
FPGA | 2 | 0 | |
EN_ADC_1_2_12V
|
FPGA | 2 | 1 |
| Label | Chip | Block | Pin | Location |
|---|---|---|---|---|
AN_CH4[1]
|
CPU | 0 | 0 | AIN 4 or Digital Input AIN 4 on CN32 Terminal |
RTC_BATT_FAIL
|
CPU | 0 | 1 | Battery failed/missing on the Battery Connector |
AN_CH0[1]
|
CPU | 0 | 4 | AIN 0 on CN32 Terminal |
AN_CH1[1]
|
CPU | 0 | 5 | AIN 1 or Digital Input AIN 1 on CN32 Terminal |
AN_CH2[1]
|
CPU | 0 | 8 | AIN 2 or Digital Input AIN 2 on CN32 Terminal |
AN_CH3[1]
|
CPU | 0 | 9 | AIN 3 or Digital Input AIN 3 on CN32 Terminal |
| CPU | 0 | 18 | CPU Board Red LED | |
| CPU | 0 | 19 | CPU Board Green LED | |
NIM_STATUS
|
CPU | 3 | 14 | Pin 13 on CN16 (XBee/Nimbelink_Socket) |
POWER_FAIL_3V
|
CPU | 4 | 0 | Power Input Failure |
FPGA_IRQ[1]
|
CPU | 4 | 1 | FPGA Interrupt input pin |
EN_RELAY_1
|
CPU | 4 | 4 | Relay 1 on CN32 Terminal |
EN_RELAY_2
|
CPU | 4 | 5 | Relay 2 on CN32 Terminal |
NIM_RESET
|
CPU | 4 | 6 | Pin 5 on CN16 (XBee/Nimbelink_Socket) |
DIO_1_OUT
|
FPGA | 5 | 0 | DIO 1 Out or PWM on CN32 Terminal |
DIO_2_OUT
|
FPGA | 5 | 1 | DIO 2 Out or PWM on CN32 Terminal |
DIO_1_IN
|
FPGA | 5 | 2 | DIO 1 In on CN32 Terminal |
DIO_2_IN
|
FPGA | 5 | 3 | DIO 2 In on CN32 Terminal |
DIO_3_IN
|
FPGA | 5 | 4 | DIO 3 In on CN32 Terminal |
DIO_6
|
FPGA | 5 | 5 | FPGA DIO 06 |
DIG_IN_1
|
FPGA | 5 | 6 | Digital In 1 on CN32 Terminal |
DIG_IN_2
|
FPGA | 5 | 7 | Digital In 2 on CN32 Terminal |
DIG_IN_3
|
FPGA | 5 | 8 | Digital In 3 on CN32 Terminal |
EN_CL_1
|
FPGA | 5 | 9 | AIN 1 4-20 mA current loop enable |
EN_CL_2
|
FPGA | 5 | 10 | AIN 2 4-20 mA current loop enable |
EN_CL_3
|
FPGA | 5 | 11 | AIN 3 4-20 mA current loop enable |
| FPGA | 5 | 12 | Reserved | |
| FPGA | 5 | 13 | Reserved | |
EN_CL_4
|
FPGA | 5 | 14 | AIN 4 4-20 mA current loop enable |
EN_HS_SW
|
FPGA | 5 | 15 | High-Side Switch or HSPWM |
EN_ADC1_12V
|
FPGA | 6 | 1 | AIN 1 0-12 V meas. mode [2] |
EN_ADC2_12V
|
FPGA | 6 | 2 | AIN 2 0-12 V meas. mode [2] |
EN_ADC3_12V
|
FPGA | 6 | 3 | AIN 3 0-12 V meas. mode [2] |
EN_ADC4_12V
|
FPGA | 6 | 4 | AIN 4 0-12 V meas. mode [2] |
EN_USB_HOST_5V
|
FPGA | 6 | 5 | en usb host 5v |
PHY_RESET#[1]
|
FPGA | 6 | 6 | Ethernet PHY reset |
WIFI_RESET#[1]
|
FPGA | 6 | 7 | WiFi module reset |
IO_RED_LED#[1]
|
FPGA | 6 | 8 | I/O Board Red LED |
IO_GREEN_LED#[1]
|
FPGA | 6 | 9 | I/O Board Green LED |
| FPGA | 6 | 12 | Reserved | |
DIO_3_OUT
|
FPGA | 6 | 13 | DIO 3 Out or PWM on CN32 Terminal |
EN_HSPWM
|
FPGA | 6 | 14 | Enable high-side PWM |
EN_LSPWM
|
FPGA | 6 | 15 | Low-side PWM drain enable |
CPU_TOUCH_IRQ#[1]
|
FPGA | 7 | 0 | Touchscreen IRQ |
| FPGA | 7 | 2 | FPGA Strapping Pin | |
| FPGA | 7 | 3 | FPGA Strapping Pin | |
| FPGA | 7 | 4 | FPGA Strapping Pin | |
| FPGA | 7 | 5 | FPGA Strapping Pin | |
NIM_3V3#_4V
|
FPGA | 7 | 6 | Data 0: Select 3.3 V power on CN16 XBee Socket [3] |
| Data 1: Select 4 V power on CN16 XBee Socket [3] | ||||
NIM_PWR_ON
|
FPGA | 7 | 8 | Pin 20 (Power Button) on CN16 XBee Socket |
SEL_NIM_USB
|
FPGA | 7 | 9 | Enable USB interface on CN16 XBee Socket [4] |
DIO_FAULT#
|
FPGA | 7 | 10 | I/O over-current/over-voltage breaker tripped [5] |
| FPGA | 7 | 11 | FPGA Strapping Pin | |
| FPGA | 7 | 12 | FPGA Strapping Pin | |
| FPGA | 7 | 13 | Reserved | |
EN_BK_LT#[1]
|
FPGA | 7 | 14 | LCD backlight enable |
- ↑ 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 Claimed by driver. Not available for use.
- ↑ 2.0 2.1 2.2 2.3 This bit is read only. Clearing the associated current loop enable bit will set this bit, setting the CL enable will clear this bit
- ↑ 3.0 3.1 To disable power on this pin, set the GPIO as an input with 'gpioset' or otherwise
- ↑ This will relocate the USB channel connected to the top USB host port
- ↑ This bit must be cleared manually after a trip to de-assert the associated IRQ
Digital Inputs
The digital inputs on the TS-7100-Z are capable of supporting various voltage ranges and input modes. The digital inputs support dry contact switches as well as a driven input voltage. The table below lists each digital input, the bank and pin number for reading the input, the maximum input voltage range, the threshold voltages, as well as the location of the input. VIH Min is the minimum voltage on the input to trigger a logic 1 input. VIL Max is the maximum voltage on the input to trigger a logic 0 input. All of the digital inputs are hysteretic. The driving input must be able to at least sink current to drive the input low, but all digital inputs are compatible with push-pull drivers.
| Input Name | Chip | Bank | Pin | V Range | VIH Min | VIL Max | Location |
|---|---|---|---|---|---|---|---|
| Digital In 1 | FPGA | 5 | 6 | 0-30 V | ~2.57 V | ~0.95 V | CN32 Terminal, pin 9 |
| Digital In 2 | FPGA | 5 | 7 | 0-30 V | ~2.57 V | ~0.95 V | CN32 Terminal, pin 11 |
| Digital In 3 | FPGA | 5 | 8 | 0-30 V | ~2.57 V | ~0.95 V | CN32 Terminal, pin 13 |
| DIO 1 In [1] | FPGA | 5 | 2 | 0-30 V | ~2.54 V | ~0.90 V | CN32 Terminal, pin 14 |
| DIO 2 In [1] | FPGA | 5 | 3 | 0-30 V | ~2.54 V | ~0.90 V | CN32 Terminal, pin 16 |
| DIO 3 In [1] | FPGA | 5 | 4 | 0-30 V | ~2.54 V | ~0.90 V | CN32 Terminal, pin 18 |
| AIN 1 In [2] | CPU | 0 | 5 | 0-12 V | ~8.60 V | ~7.90 V | CN32 Terminal, pin 25 |
| AIN 2 In [2] | CPU | 0 | 8 | 0-12 V | ~8.60 V | ~7.90 V | CN32 Terminal, pin 23 |
| AIN 3 In [2] | CPU | 0 | 9 | 0-12 V | ~8.60 V | ~7.90 V | CN32 Terminal, pin 21 |
| AIN 4 In [2] | CPU | 0 | 0 | 0-12 V | ~8.60 V | ~7.90 V | CN32 Terminal, pin 19 |
- ↑ 1.0 1.1 1.2 This GPIO should only be read as an input. Its value reflects the voltage on the physical CN32 pin, regardless of output status
- ↑ 2.0 2.1 2.2 2.3 The AIN pins can be used as Digital Inputs, but require software changes first. See the ADC section for more information
Digital Outputs
The TS-7100-Z supports a handful of digital output pins. These are able to act as high-current low-side switches. The table below lists each digital output, the bank and pin number for accessing it, the maximum voltage rating, the maximum current output, as well as the location of the pin.
| DIO Name | Chip | Bank | Pin | Max V Rating | Max A Rating | Location |
|---|---|---|---|---|---|---|
DIO_1_OUT
|
FPGA | 5 | 0 | 30 V | 700 mA (sink) [1] | CN32 Terminal, pin 14 |
DIO_2_OUT
|
FPGA | 5 | 1 | 30 V | 700 mA (sink) [1] | CN32 Terminal, pin 16 |
DIO_3_OUT
|
FPGA | 6 | 13 | 30 V | 700 mA (sink) [1] | CN32 Terminal, pin 18 |
EN_HS_SW
|
FPGA | 5 | 15 | 48 V [2] | 300 mA (source) [3] | CN32 Terminal, pin 27 |
- ↑ 1.0 1.1 1.2 Not to exceed 1000 mA total across all three Digital I/O, doing so will cause the over-current breaker to trip
- ↑ The output voltage is the same as the TS-7100-Z input voltage
- ↑ Exceeding 330 mA will cause the over-current breaker to trip
Digital Output Over-Current Breaker
The TS-7100-Z I/O PCB in combination with the FPGA on the TS-7100, implements an electronic over-current breaker. When this breaker is tripped all three DIO Out paths will be disabled, the High-Side Switch output will be disabled, analog current loops will be disabled, and the red LED on the TS-7100-Z I/O board will be illuminated. That is, digital outputs will cease to sink or source any amount of current, and the AIN inputs will have 4-20 mA input disabled. The tripped breaker will also trigger a DIO fault breaker interrupt as well as set the associated GPIO flag DIO_FAULT#. The GPIO output DIO_FAULT# must be cleared manually in order to reset the IRQ output. However, once the breaker trips, and the trip condition is cleared; all relevant GPIO settings can immediately be re-enabled without clearing this GPIO output bit.
Trip Conditions
See the table above for each DIO channel's maximum current rating. Note that the breaker does NOT enforce these ratings per DIO channel. The breaker will trip if the combined total amount of current sunk from all three digital outputs exceeds 1 A.
See the table above for the High-Side Switch's maximum current rating. If the rated max supply current is exceeded, the breaker will trip.
Note that all of these are in parallel. If the combined DIO sink current OR High-Side Switch current is exceeded, then the breaker will trip. The over-current breaker will also disable analog 4-20 mA current loop measurements.
I2C
The i.MX93 supports I2C at 100 kHz (other modes supported such as 400 kHz?). This board uses two CPU I2C busses for onboard ICs.
| Device | Address | Description |
|---|---|---|
| /dev/i2c-0 | 0x?? | NXP PMIC |
| /dev/i2c-1 | 0x10 | #SMC |
| 0x1e | #Magnetometer[1] | |
| 0x68 | #RTC | |
| 0x6a | #IMU[1] | |
| 0x?? | DisplayPort Transceiver |
IMU
Interrupts
Jumpers
LEDs
Magnetometer
MicroSD Interface
PWM
SILO
Sleep Mode
SPI
Supervisory Microcontroller
UARTs
RS-232, RS-485/422.
USB
Watchdog
WiFi
XBee/Nimbelink
Specifications
IO specifications
Power Consumption
Power Input Specifications
External Interfaces
Audio Header (HD1)
Battery Connector
CN24 Screw Terminals
Daughter Card Header
DisplayPort Connector (CN20)
Ethernet Connectors
MicroSD Connector
mikroBUS Header (CN17)
Power Connector
USB Ports
USB-C Console Connector
XBee/Nimbelink Header (CN16)
TS-9370 Revisions and Changes
PCB Revisions
U-Boot Revisions
Depending on context, you can determine your U-Boot revision in one of several ways:
1. The U-Boot build date can be viewed as the first line of USB console output when the unit is powered on. For example:
U-Boot 2016.03-00408-gd450758c91 (Oct 10 2019 - 11:59:08 -0700) CPU: Freescale i.MX6UL rev1.2 at 396 MHz ...
2. U-Boot has a version command that outputs similar version information to what is shown above.
3. At a Linux shell, the following command prints the version strings of any U-Boot and/or SPL image that is present in eMMC:
strings /dev/mmcblk0boot0 | grep '^U-Boot .*(.*)'
The output is the same string(s) that will be printed on the console at board startup.
FPGA Revisions
Supervisory Microcontroller (SMC) Firmware Revisions
Root Filesystem Software Images
Debian Changelog
See our Debian release archive for all released images, including the latest for each supported Debian version.
Product Notes
FCC Advisory
This equipment generates, uses, and can radiate radio frequency energy and if not installed and used properly (that is, in strict accordance with the manufacturer's instructions), may cause interference to radio and television reception. It has been type tested and found to comply with the limits for a Class A digital device in accordance with the specifications in Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment. Operation of this equipment in a residential area is likely to cause interference, in which case the owner will be required to correct the interference at his own expense.
If this equipment does cause interference, which can be determined by turning the unit on and off, the user is encouraged to try the following measures to correct the interference:
Reorient the receiving antenna. Relocate the unit with respect to the receiver. Plug the unit into a different outlet so that the unit and receiver are on different branch circuits. Ensure that mounting screws and connector attachment screws are tightly secured. Ensure that good quality, shielded, and grounded cables are used for all data communications. If necessary, the user should consult the dealer or an experienced radio/television technician for additional suggestions. The following booklets prepared by the Federal Communications Commission (FCC) may also prove helpful:
How to Identify and Resolve Radio-TV Interference Problems (Stock No. 004-000-000345-4) Interface Handbook (Stock No. 004-000-004505-7) These booklets may be purchased from the Superintendent of Documents, U.S. Government Printing Office, Washington, DC 20402.
Limited Warranty
See our Terms and Conditions for more details.
| WARNING: | Setting any of the eMMC's write-once registers (e.g. enabling enhanced area and/or write reliability) will immediately void ALL of our return policies and replacement warranties. This includes but is not limited to: the 45-day full money back evaluation period; any returns outside of the 45-day evaluation period; warranty returns within the 1 year warranty period that would require SBC replacement. Our 1 year limited warranty still applies, however it is at our discretion to decide if the SBC can be repaired, no warranty replacements will be provided if the OTP registers have been written. |
Trademarks
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.