TS-9370 FPGA

FPGA Registers

The TS-9370's FPGA is connected to the CPU over the FlexSPI bus. This provides 32-bit access to the FPGA, mapped at 0x2800_0000.

For example, to read the FPGA's model/rev/info block:

root@tsimx9:~# memtool md -l 0x28000000+0x40
28000000: 00009370 00000104 a5b2da72 32fce7d1                p.......r......2
28000010: 00000000 00000000 00000000 00000000                ................
28000020: 00000000 00000000 00000000 00000000                ................
28000030: 00000000 00000000 00000000 00000000                ................
root@tsimx9:~#

Offset	Description
0x0000	Model/Rev Info
0x0040	FPGA GPIO block #0
0x0080	FPGA GPIO block #1
0x00C0	FPGA GPIO block #2

FPGA GPIO Instances

Note:

Unlike GPIO into the CPU, at present the FPGA GPIOs do not support interrupts.

Each of the three GPIO blocks can manage up to 32 IO lines. The 32-bit registers controlling each block are defined as follows:

Offset	Read Function	Write Function
0x00	Output Enables	Set OE Bits
0x04	Reserved	Clear OE Bits
0x08	Output Data	Set Data Bits
0x0c	Input Data	Clear Data Bits
0x10	Reserved	Reserved
0x14	Reserved	Reserved
0x18	Reserved	Reserved
0x1c	Reserved	Reserved