TS-ADC16

TS-ADC16

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Schematic
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ADC Datasheet
DAC Datasheet

Overview

The TS-ADC16 is a 8-bit (16-bit in ARM mode) PC/104 peripheral board that provides 16 channels of 16-bit analog to digital conversion at 2x100ksps sample rate, 4 channels of 12-bit digital to analog conversion, 4 digital inputs, 4 16-bit edge counters, and 1 digital output. This PC/104 peripheral will work with nearly all PC/104 masters in 8-bit mode, and is compatible with Technologic Systems' PC/104 SBCs in 16-bit or 8-bit mode.

Features

Analog to Digital conversion

Voltage range is selected for the entire 16 ADC channels, selectable ranges are:

 -5v to 5v single or differential
 0v to 5v single or differential
 -10v to 10v single or differential
 0v to 10v single or differential

During acquisition, two channels are sampled simultaneously (one from each of the two ADC chips) and stored in channel number order to the ADC FIFO. The number of pairs of channels to be converted is configurable. The TS-ADC16 has a variable sample rate, going as high as 100ksps; a single sample is one channel from each of the two ADC chips simultaneously. The ADC conversion state machine can be started by setting the ADCCFG register or via a negative edge trigger on digital input 0. Once the ADC conversion state machine is started, it can be stopped by clearing the SYSCOM bit, or it will automatically stop if the ADC FIFO fills up.

Interrupt capable FIFO

The TS-ADC16 has internal 512x16-bit FIFO built in to the on-board PLD. The FIFO is capable of generating interrupts on the PC/104 bus which are fired at a user-selectable FIFO count level; this defaults to half-full.

The configuration registers 0x4 and 0x6 respectively labelled ADCDLY_MSB and ADCDLY_LSB define a sampling delay equal to n * 31.2ns. Using this register, the sampling rate can be adjusted from as fast as possible to two samples every ~0.54 seconds. This allows the downstream developer to adjust the sampling rate to a very fine degree such that a consistent stream of data points is attainable while avoiding a FIFO buffer overflow. Note: Delay occurs between each channel PAIR sampled.

Counters

There are 4 16-bit counters built in to the TS-ADC16. These are negative edge triggered and permanently tied to their respectively numbered digital input pins. During a read, the current counter value is latched in at the read strobe assertion. The counters are not clearable, and will loop back to 0x0 after 0xffff.

Digital to Analog conversion

The TS-ADC16 has 4 DAC outputs, each with independent gain and a maximum drive strength of 25mA. The selectable gains are:

 0v to 2.5v
 0v to 5v

Digital Inputs

There are 4 buffered digital inputs available on the TS-ADC16. These are fed in to the Counters, and digital input 0 can be used as a trigger to start the ADC conversion state machine. All 4 digital inputs are 5v tolerant.

Digital Output

There is 1 digital output on the TS-ADC16. It outputs 0 and 3.3v, and can sink/source 50mA.

Analog to Digital converter

The TS-ADC16 uses two LTC1859 ADC chips to provide two sets of 8, 16-bit ADC channels. Each of the two chips is fed the same SPI packet for each conversion. This means that channels are acquired in pairs (one channel from each chip) for each sample conversion; also voltage range, sample speed, and sample mode are applied to both chips and therefore all of the ADC input channels all have the same configuration. Each of the 16 channels has a 42kΩ input impedance in unipolar mode (0v to Xv), and 31kΩ input impedance in bipolar mode (-Xv to Xv). See the LTC1859 Datasheet for more detailed information about the ADC inputs.

Operation

The ADC conversion state machine is started by setting SYSCOM or having digital input 0 go low with EXTTRIG set. As soon as this happens, the contents of ADCCFG are latched in and samples are acquired. The ADC conversion state machine will sample from channel pair 0 to NUMCHAN set in ADCCFG. The time between each channel pair conversions is determined by: (32000000/ADCDLY)Hz. Note that exceeding 100KHz will result in the ADC chips delaying until they are ready to complete another conversion. Once the ADC conversion state machine has sampled the NUMCHAN channel, it will loop back around and start over again at channel pair 0. Writing to any of the bits in ADCCFG (except SYSCOM) will clear the FIFO completely; the ADC conversion state machine will keep running, but the next FIFO entry read will be channel 0 with the new configuration settings. The ADC conversion state machine will run until: it is stopped by clearing SYSCOM, or if the FIFO completely fills up with 512 samples.

Samples are stored in to the FIFO in channel order. Reading ADCFIFO or ADCFIFO_MSB will consume the next sample in the FIFO. If INTEN is set, an interrupt will be triggered when the FIFO count reaches the specified FFCOUNT(WO) number. This defaults to half full, 256 samples. The PC/104 IRQ number is chosen by the jumper configuration, see Jumpers for more information.

The ADCSTAT register is a read-only/write-only/read-write register. INTEN can be read/written at any time to enable or disable interrupt triggering at FFCOUNT(WO). FFHEAD is read-only, current channel available in ADCFIFO (Note: channel, not channel pair). FFCOUNT is read-only and write-only. Reading FFCOUNT(RO) will show the current FIFO count. Writing FFCOUNT(WO) will set the FIFO count at which an interrupt gets triggered if INTEN is set.

Converting a channel value to voltage is done with the following equations:

 Unipolar: (unsigned short)((vmax/65535)*value)
 Bipolar: (signed short)((vmax-vmin)/65535)*value)

It is important to used signed numbers when in bipolar mode.

Each ADC set, AD1 and AD2, can globally sample at 100 ksps and they each internally contain an analog MUX to select the sampled channel. This means for each ADC set, the actual sample rate is 100,000 / <# channels> sps. For example, with a NUMCHAN value of 0, the single channel in each ADC set can be sampled at a max of 100 ksps. With a NUMCHAN value of 1, each of the two channels in an ADC set are sampled at 50 ksps (alternating between the two) for a total combined 100 ksps for the ADC set. With a NUMCHAN value of 7, each of the eight channels in an ADC set are sampled at 1250 sps (stepping through the channels sequentially) for a total combined 100 ksps for the ADC set. This means that no matter the NUMCHAN value, the maximum throughput of each ADC set is 100 ksps, the two sets combined output 2x100 ksps.

Acquisition mode

Single Ended

In single ended mode, each channel's input voltage is compared to ground. Analog ground is tied to digital ground.

Differential

In differential mode, two input pins are used for conversion. For example, V+ is connected to AD1_0, and V- is connected to AD1_1, this means that the input pins are connected to channel 0 and 2 respectively. When reading channel 0, the value of V+ with respect to V- is returned. When reading channel 2, the value of V- with respect to V+ is returned. In the case of Bipolar mode, channel 0 would read positive voltage and channel 2 would read the negative of that voltage. In unipolar mode, channel 0 would return a positive voltage and channel 2 would return 0v.

Digital to Analog converter (DAC)

The TS-ADC16 uses an AD5327 DAC IC. This is a 4 channel, 12-bit DAC, with output ranges of 0 to 2.5 VDC or 0 to 5 VDC. Each time the DAC register is written, this data is transferred via SPI to the AD5327 IC to update its output.

Operation

In order to update any of the 4 DAC channels to a new 12-bit value, the DACCMD register is written with a new value. In this 16-bit register the channel, gain, and value information are encoded.

When using the TS-ADC16 in 16-bit PC/104 modes, writing the DACCMD register will trigger a write of the DAC and its output state will change after the SPI command to the DAC IC is completed.

If using the TS-ADC16 in 8-bit PC/104 modes, first write the lower 8-bits of the new value to register 0xE, then write the upper 8-bits (this is the channel, gain, and upper bits of the value) to register 0xF. Upon completion of the write to 0xF, the whole 16-bit contents will be transferred to the DAC IC via SPI.

Note that there must be a 1 μs delay from the DACCMD register being written (either 0xE in 16-bit modes, or 0xF in 8-bit modes) before the register can be written again! In 8-bit modes, it is safe to write 0xE and 0xF back to back, but the 1 μs timeout must be observed before writing the next value to 0xE. In 16-bit modes, there must be a 1 μs delay between subsequent writes to the DACCMD register.

Register Map

Offset	Register Name	Bits	Access	Description
0x0	BID: Board ID register	15:12	RO	Jumper status {jp4, jp3, jp2, jp1}
		11:8	RO	PLD Revision (0x5 is latest)
		7:0	RO	Board ID = 0x3e
0x2	ADCCFG ADC Config. register Writing to bits 1-8 of this register causes the system to reset	15:10	RO	Reserved
		9	RW	EXTTRIG 1 = When dig in 0 goes low, start system 0 = System must be started with SYSCOM bit
		8	RW	Global single ended/differential (OR'ed with bit 5) 1 = single ended 0 = differential
		7:6	RW	Global analog input range 00 = -5v to +5v 01 = 0v to +5v 10 = -10v to +10v 11 = 0v to +10v
		5	RW	Global single ended/differential (OR'ed with bit 8) 1 = single ended 0 = differential
		4:1	RW	NUMCHAN Max channel pair number to sample in full cycle See ADC pins
		0	RW	SYSCOM 0 = stop system/system stopped 1 = start system/system running
0x4	ADCDLY_MSB	15:8	RO	Reserved
		7:0	RW	Bits 23:16 of 24-bit pacing clock counter (32MHz clock)
0x6	ADCDLY_LSB	15:0	RW	Bits 15:0 of 24-bit pacing clock counter (32MHz clock)
0x8	ADCSTAT	15:6	RO	FFCOUNT(RO) Current FIFO count
			WO	FFCOUNT(WO) Set count level to trigger interrupt Default half full, 256 samples
		5:1	RO	FFHEAD Channel on the head of the FIFO
		0	RW	INTEN 0 = disable interrupt generation 1 = enable interrupt at FFCOUNT(RO) >= FFCOUNT(WO)
0xA	ADCFIFO	15:0	RO	16-bit ADC read data
0xC	Reserved	15:0	RO	Reserved
0xE	DACCMD	15:14	RW	DAC channel number
		13	RW	0 = 0v to +2.5v output 1 = 0v to +5v output
		12	RW	Write as 1
		11:0	RW	12-bit DAC output for selected channel
0x10	COUNT0	15:0	RO	Counter 0 value
0x12	COUNT1	15:0	RO	Counter 1 value
0x14	COUNT2	15:0	RO	Counter 2 value
0x16	COUNT3	15:0	RO	Counter 3 value
0x18	DIGIO	15:5	RO	Reserved
		4	RW	Output 0 data
		3	RO	Input 3 data
		2	RO	Input 2 data
		1	RO	Input 1 data
		0	RO	Input 0 data
0x1A	ADCFIFO_LSB (8-bit)	7:0	RO	8-bit ADC LSB read data
0x1B	ADCFIFO_MSB (8-bit)	7:0	RO	8-bit ADC MSB read data (consumes sample)

Connectors

Note: All even pins on ADX pin headers are grounds

ADC pins

ADC Channel	ADX_Y num.	ADX pin header	Channel pair
ADC ch.0	AD1_0	AD1 pin 1	0
ADC ch.1	AD2_0	AD2 pin 1
ADC ch.2	AD1_1	AD1 pin 3	1
ADC ch.3	AD2_1	AD2 pin 3
ADC ch.4	AD1_2	AD1 pin 5	2
ADC ch.5	AD2_2	AD2 pin 5
ADC ch.6	AD1_3	AD1 pin 7	3
ADC ch.7	AD2_3	AD2 pin 7
ADC ch.8	AD1_4	AD1 pin 9	4
ADC ch.9	AD2_4	AD2 pin 9
ADC ch.10	AD1_5	AD1 pin 11	5
ADC ch.11	AD2_5	AD2 pin 11
ADC ch.12	AD1_6	AD1 pin 13	6
ADC ch.13	N/A	AD2 pin 13
ADC ch.14	AD1_7	AD1 pin 15	7
ADC ch.15	N/A	AD2 pin 15

DAC pins

DAC channel	DACX num.	ADX pin header
DAC ch.0	DAC A	AD2 pin 19
DAC ch.1	DAC B	AD2 pin 21
DAC ch.2	DAC C	AD2 pin 23
DAC ch.3	DAC D	AD2 pin 25

Digital Input pins

Input num.	ADX pin header
Input 0	AD1 pin 19
Input 1	AD1 pin 21
Input 2	AD1 pin 23
Input 3	AD1 pin 25

Digital Output pin

Output num.	ADX pin header
Output 0	AD1 pin 17

Jumpers

PC/104 base address

JP2	JP1	Addr
Off	Off	0x100
Off	On	0x120
On	Off	0x140
On	On	0x160

ARM/x86 mode

JP3	PC/104 Mode
Off	8bit (x86)
On	TS ARM 16bit pinout

IRQ select

IRQ output is active high, sharable with other PC/104 devices, and will remain asserted as long as INTEN is set and the FIFO count is greater than FFCOUNT(WO)

JP4	IRQ
Off	IRQ6
On	IRQ7

Quick Start Guide

This assumes the use of the TS-7800 as the PC104 baseboard and a TS-ADC16 by itself with only JP3 installed. You will need one small screw driver (to manipulate terminal blocks), and one jumper wire long enough to stretch the complete length of the TS-ADC16 (An extra inch or two is probably a good thing). The current shipping image is used during this guide, please see the TS-7800 manual for information on restoring a TS-7800 to the stock image. Note that several different stock SBC from embeddedTS could be used. Please see your SBC's respective manual for information on PC/104 addressing.

This guide also assumes running from the fastboot shell of the TS-7800 while connected to the serial port with a terminal emulator.

Once the TS-7800 is powered up, the PC/104 bus must be enabled with the following command:

pc104on

This command will not return anything. Note that the `pc104on` command will not be needed for most embeddedTS SBC's. Please see your SBC's respective manual for information on this.

Run the following command next:

peekpoke 16 0xEF000100

The above command will return 0x453E. Please see the Register Map for a breakdown of this register. Note that 0xEF000000 is the start of the TS-7800 16bit I/O for PC/104. If you are using a different SBC, use that SBC's PC/104 base address plus 0x100 for the base of the TS-ADC16 device.

Next, run:

peekpoke 16 0xEF00010E 0x3FFF

This command will return 0x3FFF. This command is setting the DAC output of DAC_A (DAC Channel 0) to 5v, this voltage can be verified with any voltage meter. Again, Please see the Register Map for a breakdown of this register.

peekpoke 16 0xEF00010E 0x3000

This command will return 0x3000, and sets DAC_A (DAC Channel 0) to 0v.

Use a small length of wire to connect DAC_A (DAC Channel 0) to AD1_0 (ADC Channel 0), be sure to securely tighten the screw terminal at both ends. No ground wire is needed since ADC and DAC grounds are connected on the TS-ADC16 itself. Once connected, the following command will start the ADC state machine:

peekpoke 16 0xEF000102 0x161

This command will return 0x161. This sets up the ADC read and starts the ADC reading values and dumping them into the FIFO. Since the TS-ADC16 samples in channel pairs, the ADC state machine will do alternate reads of AD1_0 and AD2_0, shoving them in to the FIFO until it fills up.

The data can be read out of the FIFO with the following command:

peekpoke 16 0xEF00010A

This command will return a value close to 0x0 if the DAC_A output was left at 0v, and close to 0xFFFF if the DAC_A output was set back to 5v. The FIFO register can hold up to 512 samples total. When reading the register in this instance, the value read will change between AD1_0 and AD2_0 as stated above.

There is also a continuous 4 channel sampling externally triggered example on the FTP site on our FTP server.

If you have any further questions, please contact our support staff.

Development Notes / FAQ

What is the tsadc1624lib? Is it relevant to the TS-ADC16?
The tsadc1624lib is deprecated software and should not be used. It was designed to combine the similar functionalities between the TS-ADC16 and TS-ADC24 into one cohesive library during early development. Unfortunately there were bugs in the software and changes were made to the TS-ADC16 and TS-ADC24 that forced the development of the library to diverge too far from the original intent. The software is no longer recommended for use with either product.

Will the quick start example work with my non TS-7800 system?
Not directly. PC104 access procedure and addressing will change dramatically from one TS product to the next. It is best to understand how to access the PC104 bus on your specific SBC, then apply that knowledge to the quick start guide. The changes will be the method of "turning on" PC104 (if necessary), the command used to access memory addresses (peekpoke, devmem, etc), and the memory addresses themselves.

Can I copy/paste the example code into my application verbatim?
The examples are generalizations to demonstrate how the device functions, they are not intended to provide a useful API. Presently there are no plans to create an API for this product. Please feel free to contact sales@embeddedTS.com if you would like the TS engineering team to create an API for your team to use.

Usage with 3rd party devices

Please note that while efforts are made to follow the PC/104 specification this peripheral is not tested with third party SBCs or connected peripherals. This card is not guaranteed to operate as intended when third party PC104 peripherals or SBCs are connected.