Tsctl Hardware Map
This section documents the tsctl objects available for each board. For CPU boards, the instance numbers will correspond directly to the value to pass to the corresponding Init function. For base board and PC-104 boards, the number is relative to the peripheral board itself. To get the actual number to pass, you will need to add the relative number to the total number of instances on all boards before it. For the purpose of this calculation, the CPU board comes first, followed by the base board, followed by any PC104 boards. Since there can be multiple PC104 boards, it is necessary to know the order the boards are initialized in. However, for the existing supported boards there are only Pin and DIO which are accessible via instance 0.
TS-4200
Time 0: Linux gettimeofday() based
Bus 0: FPGA syscon registers (includes FPGA DIO registers)
Bus 1: read/write memory area for test purposes
Bus 2: MuxBus
Bus 3: caches access to TS-4200 DIO registers
Bus 4: CPU DIO bank 1 registers
Bus 5: caches CPU DIO bank 1 registers
Bus 6: CPU DIO bank 2 registers
Bus 7: caches CPU DIO bank 2 registers
Bus 8: CPU DIO bank 3 registers
Bus 9: caches CPU DIO bank 3 registers
Bus 10: 8-bit bus used by MuxBus
Bus 11: 16-bit bus used by MuxBus
Pin 0: TS-4200 pin control
DIORaw 0: CPU DIO bank 1 raw access
DIORaw 1: CPU DIO bank 2 raw access
DIORaw 2: CPU DIO bank 3 raw access
DIORaw 3: FPGA DIO raw access
DIO 0: aggregate DIO access to all banks
DIO 1: CPU DIO bank 1
DIO 2: CPU DIO bank 2
DIO 3: CPU DIO bank 3
DIO 4: FPGA DIO
TWI 0: TW_CLK on DIO 24, TW_DAT on DIO 23
TS-4500 and TS-75XX
Time 0: Linux gettimeofday() based
Time 1: FPGA 1us timer based
Bus 0: SBus (includes syscon and FPGA DIO registers)
Bus 1: read/write memory area for test purposes
Bus 2: MuxBus (only valid with OpenCore or other bitstream with MuxBus support)
Bus 3: caches FPGA DIO registers
Bus 4: CPU registers control pin functions
Bus 5: caches CPU DIO registers
Bus 6: CPU DIO registers
Bus 7: SBus Window Bus (Type 1)
Bus 8: SBus Window Bus (Type 2)
Pin 0: TS-4500 pin control
CAN 0: FPGA CAN implementation (TX on DIO 15, RX on DIO 16)
DIORaw 0: FPGA DIO raw access
DIORaw 1: CPU DIO bank raw access
DIO 0: aggregate DIO access to all banks
DIO 1: FPGA DIO
DIO 2: CPU DIO
TWI 0: TW_CLK on DIO 70, TW_DAT on DIO 69
TS-4700
Time 0: Linux gettimeofday() based
Bus 0: syscon (includes FPGA DIO registers)
Bus 1: read/write memory area for test purposes
Bus 2: MuxBus
Bus 3: CPU DIO registers
Bus 4: CAN registers
Bus 5: caches FPGA DIO registers
Bus 6: caches CPU DIO registers
Bus 7: CPU TWI registers
Bus 8: CPU MFP (pin function) registers
Bus 9: 8-bit bus used by MuxBus
Bus 10: 16-bit bus used by MuxBus
Pin 0: TS-4700 pin control
CAN 0: FPGA CAN implementation (TX on DIO 15, RX on DIO 16)
DIORaw 0: FPGA DIO raw access
DIORaw 1: CPU DIO bank raw access
DIO 0: aggregate DIO access to all banks
DIO 1: FPGA DIO
DIO 2: CPU DIO
TWI 0: TW_CLK on DIO 150, TW_DAT on DIO 149
TS-4800
Time 0: Linux gettimeofday() based
Time 1: FPGA 1us timer based
Bus 0: syscon (includes FPGA DIO registers)
Bus 1: read/write memory area for test purposes
Bus 2: MuxBus
Bus 3: CPU DIO bank 1 registers
Bus 4: CPU DIO bank 2 registers
Bus 5: CPU DIO bank 3 registers
Bus 6: CPU DIO bank 4 registers
Bus 7: CAN 0 registers
Bus 8: CAN 1 registers
Bus 9: caches FPGA DIO registers
Bus 10: caches CPU DIO bank 1
Bus 11: caches CPU DIO bank 2
Bus 12: caches CPU DIO bank 3
Bus 13: caches CPU DIO bank 4
Bus 14: Window bus into CAN 0 registers
Bus 15: Window bus into CAN 1 registers
Pin 0: TS-4800 pin control
CAN 0: FPGA CAN implementation (TX on DIO 47, RX on DIO 45)
CAN 1: FPGA CAN implementation (TX on DIO 10, RX on DIO 11)
DIORaw 0: FPGA DIO raw access
DIORaw 1: CPU DIO bank 1 raw access
DIORaw 2: CPU DIO bank 2 raw access
DIORaw 3: CPU DIO bank 3 raw access
DIORaw 4: CPU DIO bank 4 raw access
DIO 0: aggregate DIO access to all banks
DIO 1: FPGA DIO
DIO 2: CPU DIO bank 1
DIO 3: CPU DIO bank 2
DIO 4: CPU DIO bank 3
DIO 5: CPU DIO bank 4
TWI 0: uses Linux /dev/i2c-1 device
Objects
In the sub-sections below, each class is described, along with the instances of the class available for each piece of supported hardware.
AIO
WBMCP3428
Implements support for the MCP3428 A/D accessed via the Technologic Systems wishbone to MCP3428 core.
Net
Implements support for AIO objects accessed via the tsctl protocol.
Bus
This class encapsulates the functionality of a bus. This is a low-level class, and normally is only used by other classes to provide a platform independant way of accessing registers. For instance, on Cavium based boards registers such as those in the SYSCON sit behind the "SBus", an SPI based bus, while on other boards the SYSCON registers sit directly in memory mapped addresses. The Bus class abstracts away the mechanism for accessing these registers.
The Bus class has a larger number of functions than other classes (currently 32). One reason for this is the need to provide more complex functions such as read-modify writes which could be done using more basic functions but which are performance enhanced by reducing the number of function calls needed to achieve them.
Cache
Implements a bus which caches the registers on another bus. It was originally designed for the purpose of allowing synchronous DIO. This class contains a number of structures which define the range of registers to be cached, and whether each bit in each register is read-only, write-only, or read-write. Accesses to negative addresses operate on the cache at the one's complement of the address passed, while positive addresses read or write through the cache to the underlying bus.
Cavium2132S
Implements support for the "SBus" interface on boards using a Cavium CPU. These are low-cost boards which use the SBus as part of the cost reduction process.
Cavium2132SBusWindow
Implements support for the SBus window on Cavium boards. This window is a set of registers that provide access to a larger underlying address space.
MMap
Implements support for traditional memory mapped access to physical addresses. Although the interface adds overhead to what would otherwise by a simple pointer de-reference, this overhead buys the ability to transparently change underlying busses. For instance, the same code can be used to access a local Bus or one across the network. The large number of functions in the Bus class provide the ability to do more complex operations such as read-modify writes with only a single function call overhead.
Net
Implements support for Bus objects accessed via the tsctl protocol.
TSMux
Implements support for the Technologic Systems "Mux" bus. This is a bus that is implement to communicate between TS-SOCKET boards and base boards using specific pins on Connector 1 ("CN1"). This requires FPGA support, in some instances this support may not be present due to space considerations in the FPGA. Consult the documentation for your board or Technologic Systems support if you need assistance in determine if your board has MuxBus support and if not how you can switch to a bitstream that does have this support.
WBWindow
Implements support for the Technologic Systems "wishbone window" bus. This is a bus that is accessed through a set of registers that provide access to a larger underlying address space.
Window
Implements support for the Technologic Systems "window" bus. This is a bus that is accessed through a set of registers that provide access to a larger underlying address space. It is similar to the WBWindow bus, but has a different register layout.
CAN
This class encapsulates the functionality of a Controller Area Network device.
SJA1000CAN
Implements support for the SJA1000 register set.
Net
Implements support for CAN objects accessed via the tsctl protocol.
NetCANctl
Implements support for the canctl protocol accessed via the CAN API. The canctl protocol is higher performance due to the fact that it cannot be multiplexed with other objects, and runs on a separate, dedicated TCP port. This implementation does not conform to the standard nomenclature of implementation name followed by class name.
DIORaw
This class encapsulates the functionality of a "raw" DIO which presents the interface of data and direction registers.
AtmelAT91
Implements support for the Atmel AT91 DIO register set.
Cavium2132
Implements support for the Cavium 2132 DIO register set.
FreescaleIMX51
Implements support for the Freescale IMX51 DIO register set.
MarvellPXA166
Implements support for the Marvell PXA166 DIO register set.
Net
Implements support for DIORaw objects accessed via the tsctl protocol.
ts4200
Implements support for the TS-4200 FPGA DIO register set.
ts4500
Implements support for the TS-4500 FPGA DIO register set.
ts4700
Implements support for the TS-4700 FPGA DIO register set.
ts4800
Implements support for the TS-4800 FPGA DIO register set.
ts81x0
Implements support for the TS-81X0 FPGA DIO register set.
tsRelay8
Implements support for the TS-RELAY8 FPGA DIO register set.
DIO
This class encapsulates the functionality of DIO. Normally the DIO class will either rely on one or more other DIO classes, or DIORaw classes to implement its functionality. The DIO abstraction introduces the concept of synchronous versus asynchronous DIO. A synchronous DIO operation allows multiple DIOs to be read or set simultaneously, or as close to simultaneously as possible, depending on how the individual DIO bits are arranged in the registers. The DIO interface also allows for waiting for one or more DIOs to reach certain values.
Aggregate
Implements support for a single DIO which aggregates multiple other DIO objects into a single object. While individual DIO objects have DIO numbers starting at 0 and increasing to one less than the number of DIOs support by the object, the Aggregate object sequentially numbers each set of DIOs, so that the DIO number of the first DIO in the second object is accessed at the next DIO number after the logical DIO number of the last object in the previous object. This object was originally implemented to provide compatibility with the dioctl protocol, which presents a single linear view of all DIO.
Net
Implements support for DIO objects accessed via the tsctl protocol.
Physical
Implements support for DIO objects which are implemented on top of an underlying DIORaw objects.
EDIO
This class encapsulates the function of Extended DIO, that is, pins which have advanced digital input/output functions beyond simple getting and setting of values.
Pin
This class encapsulates the concept of a physical I/O pin on a chip.
Net
Implements support for Pin objects accessed via the tsctl protocol.
ts4200
Implements support for the TS-4200 pin layout.
ts4500
Implements support for the TS-4500 pin layout.
ts4700
Implements support for the TS-4700 pin layout.
ts4800
Implements support for the TS-4800 pin layout.
ts81x0
Implements support for the TS-81x0 pin layout.
System
This class encapsulates common functions available across all platforms.
Local
Implements System support for all local systems.
Net
Implements support for System objects accessed via the tsctl protocol.
Time
This class encapsulates measuring and waiting for time intervals.
Cavium2132
Implements support for using the Cavium 2132 timer for timekeeping functions.
Net
Implements support for Time objects accessed via the tsctl protocol.
System
Implements support for timekeeping using Linux API calls.
TS
Implements support for using the Technologic Systems 1 microsecond timer for timekeeping functions.
TWI
This class encapsulates Two-Wire Interface (also known as I2C) communications.
DIO
Implements TWI using bit-banged DIO.
FreescaleIMX51
Implements support for TWI using Freescale IMX 51 TWI core.
Linux
Implements support for TWI using Linux API.
MarvelPXA166
Implements support for TWI using Marvell PXA166 TWI core.
Net
Implements support for TWI objects accessed via the tsctl protocol.
SPI
This class encapsulates Serial Peripheral Interface (SPI) bus communications. SPI has a simpler interface than Bus, and has the additional ReadWrite call.
AtmelAT91
Implements support for the Atmel AT91 SPI core.
Cavium2132
Implements support for the Cavium 2132 SPI core.
Net
Implements support for SPI objects accessed via the tsctl protocol.
WB
Implements support for the Technologic Systems wishbone (FPGA) SPI core.