TS-7120 FPGA: Difference between revisions

From embeddedTS Manuals
Line 65: Line 65:
| Model ID
| Model ID
|-
|-
| rowspan=7 | 0x8 (write)
| 0x4
| 31:0
| FPGA_REV_CRC32
|-
| rowspan=7 | 0x08 (read)
| 31:20
| 31:20
| Reserved
| Reserved
Line 87: Line 91:
| ASMI Data out
| ASMI Data out
|-
|-
| rowspan=4 | 0x8 (write)
| rowspan=4 | 0x08 (write)
| 31
| 31
| Reserved
| Reserved
Line 114: Line 118:
| ASMI data in
| ASMI data in
|-
|-
| 0x9
| 0x0c
| testing
| 31:0
| Scratch regsiter
|-
| 0x10
| 31:0
| DIO bank 0 Data Set
|-
| 0x12
| 31:0
| DIO bank 0 Output Enable Set
|-
| 0x14
| 31:0
| DIO bank 0 Data Clear
|-
| 0x16
| 31:0
| DIO bank0 Output Enable clear
|-
| 0x18
| 31:0
| Reserved
|-
| rowspan=2| 0x1c
| 31:16
| Current loop PWM #1
|-
| 15:0
| Current loop PWM #0
|-
| rowspan=16 | 0x24
| 31:17
| Reserved
|-
| 16
| cpu_touch_irq IRQ
|-
| 15
| wifi_irq
|-
| 14
| gyro_int
|-
| 13
| mikro_int
|-
| 12
| TS SDcore
|-
| 11
| Opencore SPI controller #2
|-
| 10
| Opencore SPI Controller #1
|-
| 9
| Opencore SPI Controller #0
|-
| 8
| UART #8 IRQ
|-
| 7
| UART #7 IRQ
|-
| 6
| UART #6 IRQ
|-
| 5
| UART #5 IRQ
|-
| 4
| UART #4 IRQ
|-
| 3
| UART #3 IRQ
|-
| 2
| UART #2 IRQ
|-
| 1
| UART #1 IRQ
|-
| 0
| UART #0 IRQ
|-
| rowspan=2 | 0x28
| 31:16
| ADC 1
|-
| 15:0
| ADC 0
|}
|}

Revision as of 16:40, 15 January 2019

The TS-7120 FPGA is connected to the CPU over the WEIM bus. This provides 8-bit, 16-bit, or 32-bit access to the FPGA mapped at 0x5000_0000.

For example, to read the syscon 0x0: 

peekpoke 32 0x50004000
Offset Description
0x00 16550 #0
0x10 16550 #1
0x20 16550 #2
0x30 16550 #3
0x40 16550 #4
0x50 16550 #5
0x60 16550 #6
0x70 16550 #7
0x80 16550 #8
0x180 Opencore SPI controller #0
0x19c Opencore SPI controller #1
0x1b8 Opencore SPI controller #2
0x280 TS SDcore
0x4000 Syscon

Syscon

Offset Bits Description
0x0 31:0 Model ID
0x4 31:0 FPGA_REV_CRC32
0x08 (read) 31:20 Reserved
19 Toggles when data_valid ASMI output is 1
18 Illegal Erase
17 Illegal Write
16 ASMI Busy
15:8 ASMI Status out
7:0 ASMI Data out
0x08 (write) 31 Reserved
30:29
Operation
0 Read
1 Write
2 Sector Erase
3 Read Status
28:8 ASMI Address
7:0 ASMI data in
0x0c 31:0 Scratch regsiter
0x10 31:0 DIO bank 0 Data Set
0x12 31:0 DIO bank 0 Output Enable Set
0x14 31:0 DIO bank 0 Data Clear
0x16 31:0 DIO bank0 Output Enable clear
0x18 31:0 Reserved
0x1c 31:16 Current loop PWM #1
15:0 Current loop PWM #0
0x24 31:17 Reserved
16 cpu_touch_irq IRQ
15 wifi_irq
14 gyro_int
13 mikro_int
12 TS SDcore
11 Opencore SPI controller #2
10 Opencore SPI Controller #1
9 Opencore SPI Controller #0
8 UART #8 IRQ
7 UART #7 IRQ
6 UART #6 IRQ
5 UART #5 IRQ
4 UART #4 IRQ
3 UART #3 IRQ
2 UART #2 IRQ
1 UART #1 IRQ
0 UART #0 IRQ
0x28 31:16 ADC 1
15:0 ADC 0
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