4500 TS-Socket: Difference between revisions

From embeddedTS Manuals
(Created page with "Please refer to your baseboard wiki or schematics for more details on which of these pins go where. {| ! CN1 ! CN2 |- | {| class=wikitable ! Name ! Pin ! ! Pin ! Name |- | [[#F...")
 
(Change from Macrocontroller to SoM)
 
(3 intermediate revisions by one other user not shown)
Line 1: Line 1:
Please refer to your baseboard wiki or schematics for more details on which of these pins go where.
{|  
{|  
! CN1
! CN1
Line 13: Line 11:
! Name
! Name
|-
|-
| [[#FPGA JTAG|FPGA_JTAG_TMS]]
| FPGA_JTAG_TMS <ref name=FPGAJTAG>The FPGA JTAG pins are not recommended for use and are not supported.  See the [[#FPGA Programming]] section for the recommended method to reprogram the FPGA.</ref>
| 1
| 1
!
!
| 2
| 2
| [[#EXT_RESET|EXT_RESET#]]
| #EXT_RESET <ref>EXT_RESET# is an input used to reboot the CPU.  Do not drive active high, use open drain.</ref>
|-
|-
| [[#FPGA JTAG|FPGA_JTAG_TCK]]
| FPGA_JTAG_TCK <ref name=FPGAJTAG />
| 3
| 3
! C
! C
| 4
| 4
| [[#EN_USB_5V|EN_USB_5V]]
| DIO_07 <ref>On our baseboard designs this pin is typically used to toggle power to the USB 5V rail (EN_USB_5V).</ref>
|-
|-
| [[#FPGA JTAG|FPGA_JTAG_TDO]]
| FPGA_JTAG_TDO <ref name=FPGAJTAG />
| 5
| 5
! N
! N
| 6
| 6
| [[#MicroSD Card Interface|SDCARD_D2]]
| SDCARD_D2  <ref name=SDPINS>For more information on working with SD cards see the [[#SD]] section.  These pins for the SD controller are also the same pins brought out on the MicroSD socket so they cannot both be used at the same time.</ref>
|-
|-
| [[#FPGA JTAG|FPGA_JTAG_TDI]]
| FPGA_JTAG_TDI <ref name=FPGAJTAG />
| 7
| 7
! 1
! 1
| 8
| 8
| [[#MicroSD Card Interface|SDCARD_D3]]
| SDCARD_D3 <ref name=SDPINS />
|-
|-
| [[#OFF_BD_RESET|OFF_BD_RESET#]]
| OFF_BD_RESET# <ref>The off board reset is driven low to reset all peripherals.</ref>
| 9
| 9
!
!
| 10
| 10
| [[#MicroSD Card Interface|SDCARD_CMD]]
| SDCARD_CMD <ref name=SDPINS />
|-
|-
| Reserved
| Reserved
Line 47: Line 45:
!
!
| 12
| 12
| [[#MicroSD Card Interface|SDCARD_3.3V]]
| SDCARD_3.3V <ref name=SDPINS />
|-
|-
| Reserved
| Reserved
Line 53: Line 51:
! C
! C
| 14
| 14
| [[#MicroSD Card Interface|SDCARD_CLK]]
| SDCARD_CLK <ref name=SDPINS />
|-
|-
| [[#Power|POWER]]
| POWER <ref name=POWERPINS>Each pin on this connector is only rated for 500mA so every POWER pin should be connected to a 5V source.</ref>
| 15
| 15
! N
! N
| 16
| 16
| [[#Power|POWER]]
| POWER <ref name=POWERPINS />
|-
|-
| Reserved
| Reserved
Line 65: Line 63:
! 1
! 1
| 18
| 18
| [[#MicroSD Card Interface|SDCARD_D0]]
| SDCARD_D0 <ref name=SDPINS />
|-
|-
| Reserved
| Reserved
Line 71: Line 69:
!
!
| 20
| 20
| [[#MicroSD Card Interface|SDCARD_D1]]
| SDCARD_D1 <ref name=SDPINS />
|-
|-
| Reserved
| Reserved
Line 97: Line 95:
| Reserved
| Reserved
|-
|-
| [[#Power|POWER]]
| POWER <ref name=POWERPINS />
| 29
| 29
!
!
Line 119: Line 117:
! N
! N
| 36
| 36
| [[#V_BAT|V_BAT]]
| V_BAT <ref>Optionally you can connect a 3.3V battery to this pin to keep the RTC alive between reboots and while the 5V rail is down.</ref>
|-
|-
| Reserved
| Reserved
Line 151: Line 149:
| Reserved
| Reserved
|-
|-
| [[#Power|POWER]]
| POWER <ref name=POWERPINS />
| 47
| 47
! 1
! 1
Line 197: Line 195:
!
!
| 62
| 62
| [[#GND|GND]]
| Ground
|-
|-
| [[#FPGA DIO|DIO_14]]
| [[#DIO|DIO_14]]
| 63
| 63
! C
! C
| 64
| 64
| [[#FPGA DIO|DIO_34]]
| [[#DIO|DIO_34]] / [[#MUXBUS|AD_15]]
|-
|-
| [[#FPGA DIO|DIO_13]]
| [[#DIO|DIO_13]]
| 65
| 65
! N
! N
| 66
| 66
| [[#FPGA DIO|DIO_33]]
| [[#DIO|DIO_33]] / [[#MUXBUS|AD_14]]
|-
|-
| [[#FPGA DIO|DIO_12]]
| [[#DIO|DIO_12]]
| 67
| 67
! 1
! 1
| 68
| 68
| [[#FPGA DIO|DIO_32]]
| [[#DIO|DIO_32]] / [[#MUXBUS|AD_13]]
|-
|-
| [[#FPGA DIO|DIO_11]]
| [[#DIO|DIO_11]]
| 69
| 69
!
!
| 70
| 70
| [[#FPGA DIO|DIO_31]]
| [[#DIO|DIO_31]] / [[#MUXBUS|AD_12]]
|-
|-
| [[#FPGA DIO|DIO_10]]
| [[#DIO|DIO_10]]
| 71
| 71
!
!
| 72
| 72
| [[#FPGA DIO|DIO_30]]
| [[#DIO|DIO_30]] / [[#MUXBUS|AD_11]]
|-
|-
| [[#FPGA DIO|DIO_9]]
| [[#DIO|DIO_09]]
| 73
| 73
! C
! C
| 74
| 74
| [[#FPGA DIO|DIO_29]]
| [[#DIO|DIO_29]] / [[#MUXBUS|AD_10]]
|-
|-
| [[#GND|GND]]
| Ground
| 75
| 75
! N
! N
| 76
| 76
| [[#FPGA DIO|DIO_28]]
| [[#DIO|DIO_28]] / [[#MUXBUS|AD_09]]
|-
|-
| [[#FPGA DIO|DIO_8]]
| [[#DIO|DIO_08]]
| 77
| 77
! 1
! 1
| 78
| 78
| [[#FPGA DIO|DIO_27]]
| [[#DIO|DIO_27]] / [[#MUXBUS|AD_08]]
|-
|-
| [[#FPGA DIO|DIO_7]]
| [[#DIO|DIO_07]]
| 79
| 79
!
!
| 80
| 80
| [[#XNAND|NAND_D7]]
| NAND_D7 / [[#MUXBUS|AD_07]]
|-
|-
| [[#FPGA DIO|DIO_6]]
| [[#DIO|DIO_06]]
| 81
| 81
!
!
| 82
| 82
| [[#XNAND|NAND_D6]]
| NAND_D6 / [[#MUXBUS|AD_06]]
|-
|-
| [[#FPGA DIO|DIO_5]]
| [[#DIO|DIO_05]]
| 83
| 83
! C
! C
| 84
| 84
| [[#XNAND|NAND_D5]]
| NAND_D5 / [[#MUXBUS|AD_05]]
|-
|-
| [[#FPGA DIO|DIO_4]]
| [[#DIO|DIO_04]]
| 85
| 85
! N
! N
| 86
| 86
| [[#XNAND|NAND_D4]]
| NAND_D4 / [[#MUXBUS|AD_04]]
|-
|-
| [[#FPGA DIO|DIO_3]]
| [[#DIO|DIO_03]]
| 87
| 87
! 1
! 1
| 88
| 88
| [[#XNAND|NAND_D3]]
| NAND_D3 / [[#MUXBUS|AD_03]]
|-
|-
| [[#FPGA DIO|DIO_2]]
| [[#DIO|DIO_02]]
| 89
| 89
!
!
| 90
| 90
| [[#XNAND|NAND_D2]]
| NAND_D2 / [[#MUXBUS|AD_02]]
|-
|-
| [[#FPGA DIO|DIO_1]]
| [[#DIO|DIO_01]]
| 91
| 91
!
!
| 92
| 92
| [[#XNAND|NAND_D1]]
| NAND_D1 / [[#MUXBUS|AD_01]]
|-
|-
| [[#FPGA DIO|DIO_0]]
| [[#DIO|DIO_00]]
| 93
| 93
! C
! C
| 94
| 94
| [[#XNAND|NAND_D0]]
| NAND_D0 / [[#MUXBUS|AD_00]]
|-
|-
| [[#GND|GND]]
| Ground
| 95
| 95
! N
! N
| 96
| 96
| [[#FPGA DIO|DIO_26]]
| [[#DIO|DIO_26]] / [[#MUXBUS|BUS_ALE#]]
|-
|-
| Reserved
| Reserved
Line 305: Line 303:
! 1
! 1
| 98
| 98
| [[#FPGA DIO|DIO_25]]
| [[#DIO|DIO_25]] / [[#MUXBUS|BUS_DIR]]
|-
|-
| [[#FPGA DIO|DIO_23]]
| [[#DIO|DIO_23]] / [[#MUXBUS|BUS_BHE#]]
| 99
| 99
!
!
| 100
| 100
| [[#FPGA DIO|DIO_24]]
| [[#DIO|DIO_24]] / [[#MUXBUS|BUS_CS#]]
|}
|}


Line 358: Line 356:
| Reserved
| Reserved
|-
|-
| Reserved
| 3.3V <ref name=33RAIL>The System-on-Module regulates a 3.3V rail which can source up to 300mA by the baseboard.</ref>
| 13
| 13
! C
! C
Line 364: Line 362:
| Reserved
| Reserved
|-
|-
| Reserved
| Ground
| 15
| 15
! N
! N
Line 382: Line 380:
| Reserved
| Reserved
|-
|-
| [[#GND|GND]]
| Ground
| 21
| 21
!
!
Line 398: Line 396:
! N
! N
| 26
| 26
| [[#CPU DIO|MFP_49]]
| Reserved
|-
|-
| [[#GND|GND]]
| Ground
| 27
| 27
! 2
! 2
| 28
| 28
| [[#TWI|TWI_CLK]]
| [[#I2C|TWI_CLK]]
|-
|-
| [[#USB Host|HOST_USB_M]]
| [[#USB Host|HOST_USB_M]]
Line 410: Line 408:
!
!
| 30
| 30
| [[#TWI|TWI_DAT]]
| [[#I2C|TWI_DAT]]
|-
|-
| [[#USB Host|HOST_USB_P]]
| [[#USB Host|HOST_USB_P]]
Line 418: Line 416:
| Reserved
| Reserved
|-
|-
| [[#CPU Voltage Testing|CPU_CORE]]
| CPU_CORE
| 33
| 33
! C
! C
Line 436: Line 434:
| Reserved
| Reserved
|-
|-
| [[#3.3V Rail|3.3V]]
| 3.3V <ref name=33RAIL />
| 39
| 39
!
!
Line 452: Line 450:
! C
! C
| 44
| 44
| [[#CPU JTAG|CPU_JTAG_TMS]]
| CPU_JTAG_TMS
|-
|-
| [[#GND|GND]]
| Ground
| 45
| 45
! N
! N
| 46
| 46
| [[#CPU JTAG|CPU_JTAG_TCK]]
| CPU_JTAG_TCK
|-
|-
| Reserved
| Reserved
Line 464: Line 462:
! 2
! 2
| 48
| 48
| [[#CPU JTAG|CPU_JTAG_TDI]]
| CPU_JTAG_TDI
|-
|-
| Reserved
| Reserved
Line 470: Line 468:
!
!
| 50
| 50
| [[#CPU JTAG|CPU_JTAG_TDO]]
| CPU_JTAG_TDO
|-
|-
| [[#GND|GND]]
| | Ground
| 51
| 51
!
!
Line 482: Line 480:
! C
! C
| 54
| 54
| [[#FPGA DIO|DIO_50]]
| [[#DIO|DIO_50]]
|-
|-
| Reserved
| Reserved
Line 488: Line 486:
! N
! N
| 56
| 56
| [[#FPGA DIO|DIO_51]]
| [[#DIO|DIO_51]]
|-
|-
| [[#1.8V Rail|DDR_1.8V]]
| 1.8V
| 57
| 57
! 2
! 2
| 58
| 58
| [[#FPGA DIO|DIO_52]]
| [[#DIO|DIO_52]]
|-
|-
| Reserved
| Reserved
Line 500: Line 498:
!
!
| 60
| 60
| [[#FPGA DIO|DIO_43]]
| [[#DIO|DIO_43]]
|-
|-
| Reserved
| Reserved
Line 506: Line 504:
!
!
| 62
| 62
| [[#FPGA DIO|DIO_49]]
| [[#DIO|DIO_49]]
|-
|-
| [[#CPU Voltage Testing|1.2V]]
| 1.2V
| 63
| 63
! C
! C
| 64
| 64
| [[#FPGA DIO|DIO_17]]
| [[#DIO|DIO_17]]
|-
|-
| [[#FPGA DIO|DIO_48]]
| [[#DIO|DIO_48]]
| 65
| 65
! N
! N
| 66
| 66
| [[#FPGA DIO|DIO_18]]
| [[#DIO|DIO_18]]
|-
|-
| [[#SPI|SPI_MOSI]]
| [[#SPI|SPI_MOSI]]
Line 524: Line 522:
! 2
! 2
| 68
| 68
| [[#FPGA DIO|DIO_19]]
| [[#DIO|DIO_19]]
|-
|-
| [[#SPI|SPI_MISO]]
| [[#SPI|SPI_MISO]]
Line 530: Line 528:
!
!
| 70
| 70
| [[#FPGA DIO|DIO_20]]
| [[#DIO|DIO_20]]
|-
|-
| [[#SPI|SPI_CLK]]
| [[#SPI|SPI_CLK]]
Line 536: Line 534:
!
!
| 72
| 72
| [[#FPGA DIO|DIO_21]]
| [[#DIO|DIO_21]]
|-
|-
| [[#GND|GND]]
| Ground
| 73
| 73
! C
! C
Line 554: Line 552:
! 2
! 2
| 78
| 78
| [[#XUARTs|UART0_TXD(DIO_36)]]
| [[#DIO|DIO_36]] / [[#COM Ports|XUART0_TXD]]
|-
|-
| [[#CPU Voltage Testing|3.3V]]
| 3.3V <ref name=33RAIL />
| 79
| 79
!
!
| 80
| 80
| [[#XUARTs|UART0_RXD(DIO_37)]]
| [[#DIO|DIO_37]] / [[#COM Ports|UART0_RXD]]
|-
|-
| Reserved
| Reserved
Line 566: Line 564:
!
!
| 82
| 82
| [[#XUARTs|UART1_TXD(DIO_38)]]
| [[#DIO|DIO_38]] / [[#COM Ports|UART1_TXD]]
|-
|-
| Reserved
| Reserved
Line 572: Line 570:
! C
! C
| 84
| 84
| [[#XUARTs|UART1_RXD(DIO_39)]]
| | [[#DIO|DIO_39]] / [[#COM Ports|UART1_RXD]]
|-
|-
| Reserved
| Reserved
Line 578: Line 576:
! N
! N
| 86
| 86
| [[#XUARTs|UART2_TXD(DIO_22)]]
| [[#DIO|DIO_22]] / [[#COM Ports|UART2_TXD]]
|-
|-
| Reserved
| Reserved
Line 584: Line 582:
! 2
! 2
| 88
| 88
| [[#XUARTs|UART2_RXD(DIO_44)]]
| [[#DIO|DIO_44]] / [[#COM Ports|UART2_RXD]]
|-
|-
| Reserved
| Reserved
Line 590: Line 588:
!
!
| 90
| 90
| [[#XUARTs|UART3_TXD(DIO_45)]]
| [[#DIO|DIO_45]] / [[#COM Ports|UART3_TXD]]
|-
|-
| Reserved
| Reserved
Line 596: Line 594:
!
!
| 92
| 92
| [[#XUARTs|UART3_RXD(DIO_46)]]
| [[#DIO|DIO_46]] / [[#COM Ports|UART3_RXD]]
|-
|-
| [[#Debug Console|DEBUG_TXD]]
| [[#Debug Console|DEBUG_TXD]]
Line 602: Line 600:
! C
! C
| 94
| 94
| [[#XUARTs|UART4_TXD(DIO_47)]]
| [[#DIO|DIO_47]] / [[#COM Ports|UART4_TXD]]
|-
|-
| [[#Debug Console|DEBUG_RXD]]
| [[#Debug Console|DEBUG_RXD]]
Line 608: Line 606:
! N
! N
| 96
| 96
| [[#XUARTs|UART4_RXD(DIO_40)]]
| | [[#DIO|DIO_40]] / [[#COM Ports|UART4_RXD]]
|-
|-
| [[#FPGA CAN|CAN_TXD(DIO_15)]]
| [[#DIO|DIO_15]] / [[#CAN|CAN_TXD]]
| 97
| 97
! 2
! 2
| 98
| 98
| [[#XUARTs|UART5_TXD(DIO_41)]]
| [[#DIO|DIO_41]] / [[#COM Ports|UART5_TXD]]
|-
|-
| [[#FPGA CAN|CAN_RXD(DIO_16)]]
| [[#DIO|DIO_16]] / [[#CAN|CAN_RXD]]
| 99
| 99
!
!
| 100
| 100
| [[#XUARTs|UART5_RXD(DIO_42)]]
| [[#DIO|DIO_42]] / [[#COM Ports|UART5_RXD]]
|}
|}
|}
|}
<references />

Latest revision as of 11:25, 13 June 2023

CN1 CN2
Name Pin Pin Name
FPGA_JTAG_TMS [1] 1 2 #EXT_RESET [2]
FPGA_JTAG_TCK [1] 3 C 4 DIO_07 [3]
FPGA_JTAG_TDO [1] 5 N 6 SDCARD_D2 [4]
FPGA_JTAG_TDI [1] 7 1 8 SDCARD_D3 [4]
OFF_BD_RESET# [5] 9 10 SDCARD_CMD [4]
Reserved 11 12 SDCARD_3.3V [4]
Reserved 13 C 14 SDCARD_CLK [4]
POWER [6] 15 N 16 POWER [6]
Reserved 17 1 18 SDCARD_D0 [4]
Reserved 19 20 SDCARD_D1 [4]
Reserved 21 22 Reserved
Reserved 23 C 24 Reserved
Reserved 25 N 26 Reserved
Reserved 27 1 28 Reserved
POWER [6] 29 30 Reserved
Reserved 31 32 Reserved
Reserved 33 C 34 Reserved
Reserved 35 N 36 V_BAT [7]
Reserved 37 1 38 Reserved
Reserved 39 40 Reserved
Reserved 41 42 Reserved
Reserved 43 C 44 Reserved
Reserved 45 N 46 Reserved
POWER [6] 47 1 48 Reserved
Reserved 49 50 Reserved
Reserved 51 52 Reserved
Reserved 53 C 54 Reserved
Reserved 55 N 56 Reserved
Reserved 57 1 58 Reserved
Reserved 59 60 Reserved
Reserved 61 62 Ground
DIO_14 63 C 64 DIO_34 / AD_15
DIO_13 65 N 66 DIO_33 / AD_14
DIO_12 67 1 68 DIO_32 / AD_13
DIO_11 69 70 DIO_31 / AD_12
DIO_10 71 72 DIO_30 / AD_11
DIO_09 73 C 74 DIO_29 / AD_10
Ground 75 N 76 DIO_28 / AD_09
DIO_08 77 1 78 DIO_27 / AD_08
DIO_07 79 80 NAND_D7 / AD_07
DIO_06 81 82 NAND_D6 / AD_06
DIO_05 83 C 84 NAND_D5 / AD_05
DIO_04 85 N 86 NAND_D4 / AD_04
DIO_03 87 1 88 NAND_D3 / AD_03
DIO_02 89 90 NAND_D2 / AD_02
DIO_01 91 92 NAND_D1 / AD_01
DIO_00 93 C 94 NAND_D0 / AD_00
Ground 95 N 96 DIO_26 / BUS_ALE#
Reserved 97 1 98 DIO_25 / BUS_DIR
DIO_23 / BUS_BHE# 99 100 DIO_24 / BUS_CS#
Name Pin Pin Name
ETH_RX+ 1 2 ETH_LEFT_LED
ETH_RX- 3 C 4 ETH_RIGHT_LED
ETH_CT 5 N 6 RED_LED#
ETH_TX+ 7 2 8 GREEN_LED#
ETH_TX- 9 10 Reserved
ETH_CT 11 12 Reserved
3.3V [8] 13 C 14 Reserved
Ground 15 N 16 Reserved
Reserved 17 2 18 Reserved
Reserved 19 20 Reserved
Ground 21 22 Reserved
DEV_USB_M 23 C 24 Reserved
DEV_USB_P 25 N 26 Reserved
Ground 27 2 28 TWI_CLK
HOST_USB_M 29 30 TWI_DAT
HOST_USB_P 31 32 Reserved
CPU_CORE 33 C 34 Reserved
HOSTB_USB_M 35 N 36 Reserved
HOSTB_USB_P 37 2 38 Reserved
3.3V [8] 39 40 Reserved
Reserved 41 42 Reserved
Reserved 43 C 44 CPU_JTAG_TMS
Ground 45 N 46 CPU_JTAG_TCK
Reserved 47 2 48 CPU_JTAG_TDI
Reserved 49 50 CPU_JTAG_TDO
Ground 51 52 Reserved
Reserved 53 C 54 DIO_50
Reserved 55 N 56 DIO_51
1.8V 57 2 58 DIO_52
Reserved 59 60 DIO_43
Reserved 61 62 DIO_49
1.2V 63 C 64 DIO_17
DIO_48 65 N 66 DIO_18
SPI_MOSI 67 2 68 DIO_19
SPI_MISO 69 70 DIO_20
SPI_CLK 71 72 DIO_21
Ground 73 C 74 Reserved
Reserved 75 N 76 Reserved
Reserved 77 2 78 DIO_36 / XUART0_TXD
3.3V [8] 79 80 DIO_37 / UART0_RXD
Reserved 81 82 DIO_38 / UART1_TXD
Reserved 83 C 84 DIO_39 / UART1_RXD
Reserved 85 N 86 DIO_22 / UART2_TXD
Reserved 87 2 88 DIO_44 / UART2_RXD
Reserved 89 90 DIO_45 / UART3_TXD
Reserved 91 92 DIO_46 / UART3_RXD
DEBUG_TXD 93 C 94 DIO_47 / UART4_TXD
DEBUG_RXD 95 N 96 DIO_40 / UART4_RXD
DIO_15 / CAN_TXD 97 2 98 DIO_41 / UART5_TXD
DIO_16 / CAN_RXD 99 100 DIO_42 / UART5_RXD
  1. ↑ 1.0 1.1 1.2 1.3 The FPGA JTAG pins are not recommended for use and are not supported. See the #FPGA Programming section for the recommended method to reprogram the FPGA.
  2. ↑ EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain.
  3. ↑ On our baseboard designs this pin is typically used to toggle power to the USB 5V rail (EN_USB_5V).
  4. ↑ 4.0 4.1 4.2 4.3 4.4 4.5 4.6 For more information on working with SD cards see the #SD section. These pins for the SD controller are also the same pins brought out on the MicroSD socket so they cannot both be used at the same time.
  5. ↑ The off board reset is driven low to reset all peripherals.
  6. ↑ 6.0 6.1 6.2 6.3 Each pin on this connector is only rated for 500mA so every POWER pin should be connected to a 5V source.
  7. ↑ Optionally you can connect a 3.3V battery to this pin to keep the RTC alive between reboots and while the 5V rail is down.
  8. ↑ 8.0 8.1 8.2 The System-on-Module regulates a 3.3V rail which can source up to 300mA by the baseboard.
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