47xx EVGPIO
From embeddedTS Manuals
This board features the EVGPIO core (Event Driven GPIO) which allows a low bandwidth mechanism to monitor all FPGA DIO on a shared interrupt.
The most common mechanism for monitoring for changes of state among many inputs involves having software poll lots of 16-bit registers and use boolean bitwise operations to query interested pin states. An EVGPIO core is instead constantly monitoring inputs for posedges or negedges and will deliver an 8-bit opcode of the following format when a delta from the previously sent state is detected.
The EVGPIO registers follow this format:
| Bits | Usage | ||||||
|---|---|---|---|---|---|---|---|
| 7 |
| ||||||
| 6:0 | Input number |