75XX SPI
This core is for high speed SPI with auto-CS#. Starts at offset 0x40 on the this series. Chip select #0 is used for onboard spiflash on the TS-7500. Chip select #1 is used for offboard spiflash (such as the TS-752 or TS-9448. The last 2 chip selects are always available on the Cavium series boards. We also provide canctl for the common usage of spi on this series. See canctl --help for more information.
The table below is the register map for the SPI in the FPGA:
Offset | Access | Bit(s) | Description |
---|---|---|---|
0x40 | Read Only | 15 | SPI MISO state |
Read/Write | 14 | SPI CLK state | |
Read/Write | 13-10 | Speed - 0 (highest), 1 (1/2 speed), 2 (1/4 speed)... | |
Read/Write | 9-8 | LUN (0-3 representing the 4 chip selects) | |
N/A | 7-0 | Reserved | |
0x42 | Read Only | 16:0 | Previous SPI read data from last write |
0x44 | N/A | 16:0 | Reserved |
0x46 | N/A | 16:0 | Reserved |
0x48 | Read/Write | 16:0 | SPI read/write with CS# to stay asserted |
0x4a | Read Only | 16:0 | SPI pipelined read with CS# to stay asserted |
0x4c | Read/Write | 16:0 | SPI Read/Write with CS# to deassert post-op |
0x4e | N/A | 16:0 | Reserved |
The SPI clk state register should be set when CS# is deasserted. Value 0 makes SPI rising edge (CPOL=0), 1 is falling edge (CPOL=1). This only applies to speed >= 1. For speed == 0, SPI clock polarity/skew must be set from the PLL phase adjust registers in the syscon block.
Where the base clock is 75Mhz (extended temp alters this to 50Mhz), speed settings break down as follows:
0 - 75Mhz (/1) 1 - 37.5Mhz (/2) 2 - 18.75Mhz (/4) 3 - 12.5Mhz (/6) 4 - 9.375Mhz (/8) 5 - 7.5Mhz (/10) 6 - 6.25Mhz (/12) 7 - 5.36Mhz (/14) 8 - 4.68Mhz (/16) 9 - 4.17Mhz (/18) ... 15 - 2.5Mhz (/30)
Bits 10-15 were not present on TS-75XX FPGA prior to rev 4. On those TS-75XX's, SPI speed was hardcoded to 75Mhz and 75Mhz only.
The pipelined read register is for read bursts and will automatically start a subsequent SPI read upon completion of the requested SPI read. Reading from this register infers that another read will shortly follow and allows this SPI controller "a head start" on the next read for optimum read performance. This register should be accessed as long as there will be at least one more SPI read with CS# asserted to take place. This register is an appropriate target address for SBUS burst reads.