TS-7970 Terminal Blocks: Difference between revisions
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| DIO_1 ( | | DIO_1 (30 VDC I/O)<ref name=7970dio>See <source inline>DIO Usage</source> below for operational details of these I/O pins</ref> | ||
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| 6 | | 6 | ||
| DIO_2 ( | | DIO_2 (30 VDC I/O)<ref name=7970dio/> | ||
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<References /> | <References /> | ||
The DIO_1 and DIO_2 IO can be outputs, or inputs. As inputs the digital threshold is 1.2V. To guarantee low it must be < 0.5V, or for high > 2.0V. There is an internal 1.5k pullup to 5V that will bias the input high. As outputs these IO can sink up to 500mA. | '''DIO Usage''' | ||
The DIO_1 and DIO_2 IO can be outputs, or inputs. As inputs the digital threshold is 1.2V. To guarantee low it must be < 0.5V, or for high > 2.0V. When the IO is low the external device needs to sink up to 3.5mA. When the IO is high the external device needs to source 10 uA max. There is an internal 1.5k pullup to 5V that will bias the input high. As outputs these IO can sink up to 500mA. | |||
EN_DIO_1 and EN_DIO_2 outputs are controlled through FPGA DIO 249 and 250 respectively. See the [[#GPIO]] section for more information. If these pins are specified as low or in, then they are readable on FPGA reg 56 bits 7:6. | |||
DIO_1 and DIO_2 are accessed through FPGA registers. | |||
<source lang=bash> | |||
tshwctl --addr 56 --peek | |||
# read "addr56" into bash variable | |||
eval $(tshwctl --addr 56 --peek) | |||
# Read bit 7 for DIO1 | |||
echo $(($addr56 >> 7)) | |||
# Read bit 6 for DIO2 | |||
echo $((($addr56 >> 6) & 0x1)) | |||
</source> |
Latest revision as of 11:42, 19 October 2021
The TS-7970 includes two removable terminal blocks (OSTTJ0811030) for power, UARTs, CAN, and other general purpose IO.
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DIO Usage
The DIO_1 and DIO_2 IO can be outputs, or inputs. As inputs the digital threshold is 1.2V. To guarantee low it must be < 0.5V, or for high > 2.0V. When the IO is low the external device needs to sink up to 3.5mA. When the IO is high the external device needs to source 10 uA max. There is an internal 1.5k pullup to 5V that will bias the input high. As outputs these IO can sink up to 500mA.
EN_DIO_1 and EN_DIO_2 outputs are controlled through FPGA DIO 249 and 250 respectively. See the #GPIO section for more information. If these pins are specified as low or in, then they are readable on FPGA reg 56 bits 7:6.
DIO_1 and DIO_2 are accessed through FPGA registers.
tshwctl --addr 56 --peek
# read "addr56" into bash variable
eval $(tshwctl --addr 56 --peek)
# Read bit 7 for DIO1
echo $(($addr56 >> 7))
# Read bit 6 for DIO2
echo $((($addr56 >> 6) & 0x1))