TS-8551-socket: Difference between revisions

From embeddedTS Manuals
(Initial creation, has a lot of incorrect data still.)
 
m (Links auto-updated for 2022 re-branding ( https://cdn.embeddedarm.com/resource-attachments/cn-tssocket-m-spec.pdf →‎ https://cdn.embeddedTS.com/resource-attachments/cn-tssocket-m-spec.pdf))
 
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Line 1: Line 1:
The TS-SOCKET SoM devices all use 2 high density 100 pin connectors for power and all I/O.  These follow a common pinout for various external interfaces so new modules can be switched in to an application in order to lower power consumption or use a more powerful processor. The male connector is on the baseboard, and the female connector is on the SoM. The datasheet for the baseboard's male connector can be found [https://cdn.embeddedarm.com/resource-attachments/cn-tssocket-m-spec.pdf here]. Connectors can be ordered from the SoM's product page as <source inline>CN-TSSOCKET-M-10</source> for a 10 pack, or <source inline>CN-TSSOCKET-M-100</source> for 100 pieces, or from the vendor of your choice; the part is an FCI <source inline>61083-102402LF</source>.
The TS-SOCKET SoM devices all use 2 high density 100 pin connectors for power and all I/O.  These follow a common pinout for various external interfaces so new modules can be switched in to an application in order to lower power consumption or use a more powerful processor. The male connector is on the baseboard, and the female connector is on the SoM. The datasheet for the baseboard's male connector can be found [https://cdn.embeddedTS.com/resource-attachments/cn-tssocket-m-spec.pdf here]. Connectors can be ordered from the SoM's product page as <source inline>CN-TSSOCKET-M-10</source> for a 10 pack, or <source inline>CN-TSSOCKET-M-100</source> for 100 pieces, or from the vendor of your choice; the part is an FCI <source inline>61083-102402LF</source>.


[[File:TS-Socket connector photo.jpg|300px|right|TS-Socket]]
[[File:TS-Socket connector photo.jpg|300px|right|TS-Socket]]
Line 7: Line 7:


[[File:ExampleBoard.png|600px|Example Baseboard]]
[[File:ExampleBoard.png|600px|Example Baseboard]]


On the TS-8551, the entirety of both high-density connectors are broken out in to 0.1" spaced 2x25 pin headers. There are 4 of these in total, one each for CN1 odd numbered pins, CN1 even numbered pins, CN2 even numbered pins, and CN2 odd numbered pins. They are labeled on the silkscreen every 10 pins, with the first 2 and last 2 pins also being labeled.
On the TS-8551, the entirety of both high-density connectors are broken out in to 0.1" spaced 2x25 pin headers. There are 4 of these in total, one each for CN1 odd numbered pins, CN1 even numbered pins, CN2 even numbered pins, and CN2 odd numbered pins. They are labeled on the silkscreen every 10 pins, with the first 2 and last 2 pins also being labeled.
Note that the below pinout is from the perspective of the TS-8551. However, the links for each pin will link to the relevant section in this manual. When designing a custom baseboard, it is advised to consider both the TS-8551's TS-SOCKET pinout and functions as well as the target SoM's pinout. For details on a specific SoM's interface, see that device's manual.


{|  
{|  
Line 26: Line 29:
!
!
| 2
| 2
| EXT_RESET# <ref>EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain. </ref>
| EXT_RESET# <ref>EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain. </ref>
|-
|-
| FPGA_JTAG_TCK <ref name=FPGAJTAG />
| FPGA_JTAG_TCK <ref name=FPGAJTAG />
Line 32: Line 35:
! C
! C
| 4
| 4
| [[#FPGA_GPIO_Table|EN_USB_5V]] <ref>This is an output which can be manipulated as a GPIO. This pin can optionally be connected to control a FET to a separate 5 V rail for USB to allow software to reset USB devices. Many of our baseboards implement this.</ref>
| [[#USB_Host|EN_USB_5V]] <ref>This is an output which can be manipulated as a GPIO. This pin can optionally be connected to control a FET to a separate 5 V rail for USB to allow software to reset USB devices.</ref>
|-
|-
| FPGA_JTAG_TDO <ref name=FPGAJTAG />
| FPGA_JTAG_TDO <ref name=FPGAJTAG />
Line 52: Line 55:
| NC
| NC
|-
|-
| Microcontroller C2 CLK <ref name="C2">This interface is for programming the on-board microcontroller, this should be left unconnected on a baseboard.</ref>
| Microcontroller C2 CLK <ref name="C2">This interface is for programming the on-board microcontroller of the SoM, this should be left unconnected on a baseboard.</ref>
| 11
| 11
!
!
Line 64: Line 67:
| NC
| NC
|-
|-
| [[#Power_Specification|5 V Power Input]] <ref name=powerpins>The power pins should each be provided with a 5 V source.</ref>
| [[#Power_Specification|5 V Power to SoM]] <ref name=powerpins>The power pins should each be provided with a 5 V source.</ref>
| 15
| 15
! N
! N
| 16
| 16
| [[#Power_Specification|5 V Power Input]] <ref name=powerpins />
| [[#Power_Specification|5 V Power to SoM]] <ref name=powerpins />
|-
|-
| [[#CPU_GPIO_Table|CPU SPARE_1]], [[#FPGA_GPIO_Table|FPGA SPARE_1]] <ref>This is a multi-purpose pin, part of the [[#Crossbar|FPGA Crossbar MUX]]. The CPU and FPGA pins are connected in parallel.</ref>
| [[#Jumpers|No Charge Jumper]] / [[#GPIO|GPIO]] <ref>Connect to a 1 kohm pull down to disable [[#TS-SILO_Supercapacitors|Supercapacitor charging]] on compatible SoMs. Can be used as GPIO after boot.</ref>
| 17
| 17
! 1
! 1
Line 76: Line 79:
| NC
| NC
|-
|-
| [[#FPGA_GPIO_Table|DIO_43]]
| [[#Jumpers|U-Boot Jumper]] / [[#GPIO|GPIO]] <ref>Connect to a 1 kohm pull down to [[#Entering_U-Boot_Shell|enter the U-Boot shell]] at power on on compatible SoMs. Can be used as GPIO after boot.</ref>
| 19
| 19
!
!
Line 82: Line 85:
| NC
| NC
|-
|-
| [[#FPGA_GPIO_Table|DIO_44]]
| [[#GPIO|GPIO]]
| 21
| 21
!
!
| 22
| 22
| FORCE_PWR_ON# <ref>When low, overrides the microcontroller power control and enables 5 V rail on the TS-4100. Leave unconnected for normal use.</ref>
| FORCE_PWR_ON# <ref>When low, overrides the microcontroller power control and enables 5 V rail on the SoM. Leave unconnected for normal use.</ref>
|-
|-
| [[#CPU_GPIO_Table|LCD_D10]]
| [[#GPIO|GPIO]]
| 23
| 23
! C
! C
| 24
| 24
| [[#FPGA_GPIO_Table|DIO_41]]
| [[#GPIO|GPIO]]
|-
|-
| [[#CPU_GPIO_Table|LCD_D11]]
| [[#GPIO|GPIO]]
| 25
| 25
! N
! N
| 26
| 26
| [[#FPGA_GPIO_Table|DIO_42]]
| [[#GPIO|GPIO]]
|-
|-
| [[#CPU_GPIO_Table|LCD_D12]]
| [[#GPIO|GPIO]]
| 27
| 27
! 1
! 1
| 28
| 28
| [[#CPU_GPIO_Table|LCD_D02]]
| [[#GPIO|GPIO]]
|-
|-
| [[#Power_Specification|5 V Power Input]] <ref name=powerpins />
| [[#Power_Specification|5 V Power to SoM]] <ref name=powerpins />
| 29
| 29
!
!
| 30
| 30
| [[#CPU_GPIO_Table|LCD_D03]]
| [[#GPIO|GPIO]]
|-
|-
| [[#CPU_GPIO_Table|LCD_D13]]
| [[#GPIO|GPIO]]
| 31
| 31
!
!
| 32
| 32
| [[#CPU_GPIO_Table|LCD_D04]]
| [[#GPIO|GPIO]]
|-
|-
| [[#CPU_GPIO_Table|LCD_D14]]
| [[#GPIO|GPIO]]
| 33
| 33
! C
! C
| 34
| 34
| [[#CPU_GPIO_Table|LCD_D05]]
| [[#GPIO|GPIO]]
|-
|-
| [[#CPU_GPIO_Table|LCD_D15]]
| [[#GPIO|GPIO]]
| 35
| 35
! N
! N
| 36
| 36
| [[#RTC|V_BAT]]
| [[#Battery_Backed_RTC|V_BAT]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_45]]
| [[#GPIO|GPIO]]
| 37
| 37
! 1
! 1
| 38
| 38
| [[#CPU_GPIO_Table|LCD_D06]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_46]]
| [[#GPIO|GPIO]]
| 39
| 39
!
!
| 40
| 40
| [[#CPU_GPIO_Table|LCD_D07]]
| [[#GPIO|GPIO]]
|-
|-
| [[#CPU_GPIO_Table|LCD_D18]]
| [[#GPIO|GPIO]]
| 41
| 41
!
!
| 42
| 42
| [[#CPU_GPIO_Table|LCD_D21]]
| [[#GPIO|GPIO]]
|-
|-
| [[#CPU_GPIO_Table|LCD_D19]]
| [[#GPIO|GPIO]]
| 43
| 43
! C
! C
| 44
| 44
| [[#CPU_GPIO_Table|LCD_D22]]
| [[#GPIO|GPIO]]
|-
|-
| [[#CPU_GPIO_Table|LCD_D20]]
| [[#GPIO|GPIO]]
| 45
| 45
! N
! N
| 46
| 46
| [[#CPU_GPIO_Table|LCD_D23]]
| [[#GPIO|GPIO]]
|-
|-
| [[#Power_Specification|5 V Power Input]] <ref name=powerpins />
| [[#Power_Specification|5 V Power to SoM]] <ref name=powerpins />
| 47
| 47
! 1
! 1
| 48
| 48
| [[#FPGA_GPIO_Table|EN_LCD_3.3V]] <ref>This is an output that can be manipulated as a GPIO.</ref>
| [[#GPIO|GPIO]]
|-
|-
| [[#CPU_GPIO_Table|LCD_CLK]]
| [[#GPIO|GPIO]]
| 49
| 49
!
!
Line 172: Line 175:
| [[#USB_OTG|USB_OTG_5V]] <ref name=usbotg5v>Allows the [[#Supervisory_Microcontroller|supervisory microcontroller]] to measure USB VBUS for the OTG port.</ref>
| [[#USB_OTG|USB_OTG_5V]] <ref name=usbotg5v>Allows the [[#Supervisory_Microcontroller|supervisory microcontroller]] to measure USB VBUS for the OTG port.</ref>
|-
|-
| [[#CPU_GPIO_Table|LCD_HSYNC]]
| [[#GPIO|GPIO]]
| 51
| 51
!
!
| 52
| 52
| BOOT_MODE_0 <ref>When held high during CPU startup, enables i.MX6UL USB Boot bootloader.</ref>
| BOOT_MODE_0 <ref>Normally NC or pulled to ground via 1 kohm resistor. Optionally can be switched/jumpered to pull to 3.3 V through a 1 kohm resistor; this allows other booting options provided by SoM. Not all SoMs honor this pin.</ref>
|-
|-
| [[#CPU_GPIO_Table|LCD_VSYNC]]
| [[#GPIO|GPIO]]
| 53
| 53
! C
! C
Line 184: Line 187:
| NC
| NC
|-
|-
| [[#CPU_GPIO_Table|LCD_DE]]
| [[#GPIO|GPIO]]
| 55
| 55
! N
! N
Line 190: Line 193:
| NC
| NC
|-
|-
| [[#PWM|PWM]]
| [[#GPIO|GPIO]]
| 57
| 57
! 1
! 1
| 58
| 58
| [[#FPGA_GPIO_Table|DIO_39]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_16]]
| [[#GPIO|GPIO]]
| 59
| 59
!
!
| 60
| 60
| [[#FPGA_GPIO_Table|DIO_38]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_15]]
| [[#GPIO|GPIO]]
| 61
| 61
!
!
Line 208: Line 211:
| Ground
| Ground
|-
|-
| [[#FPGA_GPIO_Table|DIO_14]]
| [[#GPIO|GPIO]]
| 63
| 63
! C
! C
| 64
| 64
| [[#FPGA_GPIO_Table|DIO_37]] / [[#ZPU_MUXBUS|MUX_AD_15]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_13]]
| [[#GPIO|GPIO]]
| 65
| 65
! N
! N
| 66
| 66
| [[#FPGA_GPIO_Table|DIO_36]] / [[#ZPU_MUXBUS|MUX_AD_14]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_12]]
| [[##TS-8551_Mappings|RS-485 TX Enable]] / [[#GPIO|GPIO]]
| 67
| 67
! 1
! 1
| 68
| 68
| [[#FPGA_GPIO_Table|DIO_35]] / [[#ZPU_MUXBUS|MUX_AD_13]]
| [[#GPIO|GPIO]]
|-
|-
| [[#CAN|CAN1 RXD]]
| [[#GPIO|GPIO]]
| 69
| 69
!
!
| 70
| 70
| [[#FPGA_GPIO_Table|DIO_34]] / [[#ZPU_MUXBUS|MUX_AD_12]]
| [[#GPIO|GPIO]]
|-
|-
| [[#CAN|CAN1 TXD]]
| [[#GPIO|GPIO]]
| 71
| 71
!
!
| 72
| 72
| [[#FPGA_GPIO_Table|DIO_33]] / [[#ZPU_MUXBUS|MUX_AD_11]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_09]]  
| [[#Entering_U-Boot_Shell|U-Boot Push Switch]] / [[#GPIO|GPIO]]
| 73
| 73
! C
! C
| 74
| 74
| [[#FPGA_GPIO_Table|DIO_32]] / [[#ZPU_MUXBUS|MUX_AD_10]]
| [[#GPIO|GPIO]]
|-
|-
| Ground
| Ground
Line 248: Line 251:
! N
! N
| 76
| 76
| [[#FPGA_GPIO_Table|DIO_31]] / [[#ZPU_MUXBUS|MUX_AD_09]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_08]]
| [[#GPIO|GPIO]]
| 77
| 77
! 1
! 1
| 78
| 78
| [[#FPGA_GPIO_Table|DIO_30]] / [[#ZPU_MUXBUS|MUX_AD_08]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_07]]
| [[#GPIO|GPIO]]
| 79
| 79
!
!
| 80
| 80
| [[#FPGA_GPIO_Table|DIO_29]] / [[#ZPU_MUXBUS|MUX_AD_07]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_06]]
| [[#GPIO|GPIO]]
| 81
| 81
!
!
| 82
| 82
| [[#FPGA_GPIO_Table|DIO_28]] / [[#ZPU_MUXBUS|MUX_AD_06]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_05]]
| [[#Baseboard_ID|Board ID Data Out to SoM]]
| 83
| 83
! C
! C
| 84
| 84
| [[#FPGA_GPIO_Table|DIO_27]] / [[#ZPU_MUXBUS|MUX_AD_05]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_04]]
| [[#GPIO|GPIO]]
| 85
| 85
! N
! N
| 86
| 86
| [[#FPGA_GPIO_Table|DIO_26]] / [[#ZPU_MUXBUS|MUX_AD_04]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_03]] / [[#FPGA_Registers|Offboard Clock]]
| [[#GPIO|GPIO]]
| 87
| 87
! 1
! 1
| 88
| 88
| [[#FPGA_GPIO_Table|DIO_25]] / [[#ZPU_MUXBUS|MUX_AD_03]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_02]]
| [[#GPIO|GPIO]]
| 89
| 89
!
!
| 90
| 90
| [[#FPGA_GPIO_Table|DIO_24]] / [[#ZPU_MUXBUS|MUX_AD_02]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_01]]
| [[#GPIO|GPIO]]
| 91
| 91
!
!
| 92
| 92
| [[#FPGA_GPIO_Table|DIO_23]] / [[#ZPU_MUXBUS|MUX_AD_01]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_00]]
| [[#GPIO|GPIO]]
| 93
| 93
! C
! C
| 94
| 94
| [[#FPGA_GPIO_Table|DIO_22]] / [[#ZPU_MUXBUS|MUX_AD_00]]
| [[#GPIO|GPIO]]
|-
|-
| Ground
| Ground
Line 308: Line 311:
! N
! N
| 96
| 96
| [[#FPGA_GPIO_Table|DIO_21]] / [[#ZPU_MUXBUS|BUS_ALE#]]
| [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_17]] / [[#ZPU_MUXBUS|BUS_WAIT#]]
| [[#GPIO|GPIO]]
| 97
| 97
! 1
! 1
| 98
| 98
| [[#FPGA_GPIO_Table|DIO_20]] / [[#Booting up the board|SD Boot Jumper]] / [[#ZPU_MUXBUS|BUS_DIR]]
| [[#Jumpers|SD Boot Jumper]] <ref>Pull to ground through 1 kohm resistor to boot to SD. Leave floating to boot from on-board media. Do '''not''' connect directly to ground or 3.3 V or [[#Baseboard_ID|baseboard ID]] will no longer function.</ref> / [[#GPIO|GPIO]]
|-
|-
| [[#FPGA_GPIO_Table|DIO_18]] / [[#MUXBUS|BUS_BHE#]]
| [[#GPIO|GPIO]]
| 99
| 99
!
!
| 100
| 100
| [[#FPGA_GPIO_Table|DIO_19]] / [[#MUXBUS|BUS_CS#]]
| [[#GPIO|GPIO]]
|}
|}


Line 331: Line 334:
! Name
! Name
|-
|-
| [[#Ethernet|eth1 RX+]]
| [[#Ethernet|Port 0 RX+]] <ref name=100ongig>The Ethernet jack on the TS-8551 is rated for 1000Base-T operation, but is compatible with 10/100Base-TX PHYs</ref> / [[#Ethernet|Port 0 BD_DA+]]
| 1
| 1
!
!
| 2
| 2
| [[#Ethernet|eth1 ACT_LED]]
| [[#Ethernet|Port 0 ACT_LED]]
|-
|-
| [[#Ethernet|eth1 RX-]]
| [[#Ethernet|Port 0 RX-]] <ref name=100ongig/> / [[#Ethernet|Port 0 BD_DA-]]
| 3
| 3
! C
! C
| 4
| 4
| [[#Ethernet|eth1 SPEED_LED]]
| [[#Ethernet|Port 0 SPEED_LED]]
|-
|-
| [[#Ethernet|eth1 CT]]
| [[#Ethernet|Port 0 CT]]
| 5
| 5
! N
! N
Line 349: Line 352:
| [[#LEDs|RED_LED#]]
| [[#LEDs|RED_LED#]]
|-
|-
| [[#Ethernet|eth1 TX+]]
| [[#Ethernet|Port 0 TX+]] <ref name=100ongig/> / [[#Ethernet|Port 0 BD_DB+]]
| 7
| 7
! 2
! 2
Line 355: Line 358:
| [[#LEDs|GREEN_LED#]]
| [[#LEDs|GREEN_LED#]]
|-
|-
| [[#Ethernet Port|eth1 TX-]]
| [[#Ethernet|Port 0 TX-]] <ref name=100ongig/> / [[#Ethernet|Port 0 BD_DB-+]]
| 9
| 9
!
!
| 10
| 10
| [[#LEDs|eth0 ACT_LED]]
| [[#Ethernet|Port 1 ACT_LED]]
|-
|-
| [[#Ethernet|eth1 CT]]
| [[#Ethernet|Port 0 CT]]
| 11
| 11
!
!
| 12
| 12
| [[#CPU_GPIO_Table|CPU GPIO 0_1]]
| [[#GPIO|GPIO]]
|-
|-
| [[#Power_Output|3.3 VDC output]]
| [[#Power_Output|3.3 VDC output from SoM]]
| 13
| 13
! C
! C
Line 377: Line 380:
! N
! N
| 16
| 16
| [[#Ethernet|eth0 RX+]]
| [[#Ethernet|Port 1 RX+]]
|-
|-
| NC
| [[#Ethernet|Port 0 BD_DC+]]
| 17
| 17
! 2
! 2
| 18
| 18
| [[#Ethernet|eth0 RX-]]
| [[#Ethernet|Port 1 RX-]]
|-
|-
| NC
| [[#Ethernet|Port 0 BD_DC-]]
| 19
| 19
!
!
| 20
| 20
| [[#Ethernet|eth0 CT]]
| [[#Ethernet|Port 1 CT]]
|-
|-
| Ground
| Ground
Line 395: Line 398:
!
!
| 22
| 22
| [[#Ethernet|eth0 TX+]]
| [[#Ethernet|Port 1 TX+]]
|-
|-
| NC
| [[#Ethernet|Port 0 BD_DD+]]
| 23
| 23
! C
! C
| 24
| 24
| [[#Ethernet|eth0 TX-]]
| [[#Ethernet|Port 1 TX-]]
|-
|-
| NC
| [[#Ethernet|Port 0 BD_DD-]]
| 25
| 25
! N
! N
Line 415: Line 418:
| [[#I2C|I2C CLK]]
| [[#I2C|I2C CLK]]
|-
|-
| [[#USB Host|USB_HOST_M]]
| [[#USB_Host|USB_HOST_M]]
| 29
| 29
!
!
Line 421: Line 424:
| [[#I2C|I2C DAT]]
| [[#I2C|I2C DAT]]
|-
|-
| [[#USB|USB_HOST_P]]
| [[#USB_Host|USB_HOST_P]]
| 31
| 31
!
!
| 32
| 32
| [[#CPU_GPIO_Table|Camera PIXCLK]]
| [[#GPIO|GPIO]]
|-
|-
| Ground
| Ground
Line 431: Line 434:
! C
! C
| 34
| 34
| [[#CPU_GPIO_Table|Camera MCLK]]
| [[#GPIO|GPIO]]
|-
|-
| [[#USB OTG|USB_OTG_M]]
| [[#USB OTG|USB_OTG_M]]
Line 437: Line 440:
! N
! N
| 36
| 36
| [[#I2S Audio|I2S CLK]]
| CPU_JTAG_TDI <ref name=CPUJTAG>The CPU JTAG pins are not recommended for use and are not supported.</ref>
|-
|-
| [[#USB OTG|USB_OTG_P]]
| [[#USB OTG|USB_OTG_P]]
Line 443: Line 446:
! 2
! 2
| 38
| 38
| [[#I2S Audio|I2S FRM]]
| CPU_JTAG_TDO <ref name=CPUJTAG/>
|-
|-
| [[#Power_Output|3.3 VDC output]]
| [[#Power_Output|3.3 VDC output from SoM]]
| 39
| 39
!
!
| 40
| 40
| [[#I2S Audio|I2S TXD]]
| CPU_JTAG_TRST# <ref name=CPUJTAG/>
|-
|-
| NC
| [[#SATA|SATA TX+]]
| 41
| 41
!
!
| 42
| 42
| [[#I2S Audio|I2S RXD]]
| CPU_JTAG_TCK <ref name=CPUJTAG/>
|-
|-
| NC
| [[#SATA|SATA TX-]]
| 43
| 43
! C
! C
Line 467: Line 470:
! N
! N
| 46
| 46
| [[#CPU_GPIO_Table|En. ethernet PHY pwr]]
| NC
|-
|-
| NC
| [[#SATA|SATA RX-]]
| 47
| 47
! 2
! 2
Line 475: Line 478:
| NC
| NC
|-
|-
| NC
| [[#SATA|SATA RX+]]
| 49
| 49
!
!
Line 485: Line 488:
!
!
| 52
| 52
| [[#CPU_GPIO_Table|Camera D0]]
| [[#GPIO|GPIO]]
|-
|-
| NC
| NC
Line 491: Line 494:
! C
! C
| 54
| 54
| [[#I2S Audio|I2S MCLK]]
| CPU_JTAG_TMS <ref name=CPUJTAG/>
|-
|-
| NC
| NC
Line 497: Line 500:
! N
! N
| 56
| 56
| [[#CPU_GPIO_Table|Camera D1]]
| [[#GPIO|GPIO]]
|-
|-
| NC
| [[#SATA|SSD_PRESENT#]]
| 57
| 57
! 2
! 2
| 58
| 58
| [[#CPU_GPIO_Table|Camera D2]]
| [[#GPIO|GPIO]]
|-
|-
| NC
| NC
Line 509: Line 512:
!
!
| 60
| 60
| [[#CPU_GPIO_Table|Camera D3]]
| [[#GPIO|GPIO]]
|-
|-
| NC
| NC
Line 515: Line 518:
!
!
| 62
| 62
| [[#CPU_GPIO_Table|Camera D4]]
| [[#GPIO|GPIO]]
|-
|-
| NC
| [[#Power_Output|1.8 VDC output from SoM]] <ref>Not output from every SoM.</ref>
| 63
| 63
! C
! C
| 64
| 64
| [[#CPU_GPIO_Table|Camera D5]]
| [[#GPIO|GPIO]]
|-
|-
| [[#SPI|Off-board SPI CS#]]
| [[#SPI|SPI CS#]]
| 65
| 65
! N
! N
| 66
| 66
| [[#CPU_GPIO_Table|Camera D6]]
| [[#GPIO|GPIO]]
|-
|-
| [[#SPI|Off-board SPI MOSI]]
| [[#SPI|SPI MOSI]]
| 67
| 67
! 2
! 2
| 68
| 68
| [[#CPU_GPIO_Table|Camera D7]]
| [[#GPIO|GPIO]]
|-
|-
| [[#SPI|Off-board SPI MISO]]
| [[#SPI|SPI MISO]]
| 69
| 69
!
!
| 70
| 70
| [[#CPU_GPIO_Table|Camera HSYNC]]
| [[#GPIO|GPIO]]
|-
|-
| [[#SPI|Off-board SPI CLK]]
| [[#SPI|SPI CLK]]
| 71
| 71
!
!
| 72
| 72
| [[#CPU_GPIO_Table|Camera VSYNC]]
| [[#GPIO|GPIO]]
|-
|-
| Ground
| Ground
Line 563: Line 566:
! 2
! 2
| 78
| 78
| [[#UARTs|UART3 TXD]] ([[#Crossbar|UARTA TXD]]) <ref name="cbar">This pin is part of the FPGA Crossbar MUX. Its default Crossbar assignment is listed first, with the Crossbar name in parenthesis.</ref>
| [[#TS-8551_Mappings|UART0 TXD]] <ref name=nottl>Do '''not''' connect to the TTL interface for this UART that is present on the CN breakout pin headers. Doing so may damage the SoM or the connected hardware</ref>
|-
|-
| Reserved
| [[#Power_Output|3.3 VDC output from SoM]]
| 79
| 79
!
!
| 80
| 80
| [[#UARTs|UART3 RXD]] ([[#Crossbar|UARTA RXD]]) <ref name="cbar" />
| [[#TS-8551_Mappings|UART0 RXD]] <ref name=nottl/>
|-
|-
| [[#TS-SILO Supercapacitors|SuperCap V+]]
| [[#TS-SILO Supercapacitors|SuperCap V+]]
Line 575: Line 578:
!
!
| 82
| 82
| [[#UARTs|UART1 TXD]]
| [[#TS-8551_Mappings|UART1 TXD]] <ref name=nottl/>
|-
|-
| [[#TS-SILO Supercapacitors|SuperCap V+]]
| [[#TS-SILO Supercapacitors|SuperCap V+]]
Line 581: Line 584:
! C
! C
| 84
| 84
| [[#UARTs|UART1 RXD]]
| [[#TS-8551_Mappings|UART1 RXD]] <ref name=nottl/>
|-
|-
| Ground
| Ground
Line 587: Line 590:
! N
! N
| 86
| 86
| [[#UARTs|UART6 TXD]] ([[#Crossbar|UARTB TXD]]) <ref name="cbar" />
| [[#TS-8551_Mappings|UART2 TXD]]
|-
|-
| [[#TS-SILO Supercapacitors|SuperCap Junction]]
| [[#TS-SILO Supercapacitors|SuperCap Junction]]
Line 593: Line 596:
! 2
! 2
| 88
| 88
| [[#UARTs|UART6 RXD]] ([[#Crossbar|UARTB RXD]]) <ref name="cbar" />
| [[#TS-8551_Mappings|UART2 RXD]]
|-
|-
| [[#TS-SILO Supercapacitors|SuperCap Balance Drive]]
| [[#TS-SILO Supercapacitors|SuperCap Balance Drive]]
Line 599: Line 602:
!
!
| 90
| 90
| [[#UARTs|UART4 TXD]]
| [[#TS-8551_Mappings|UART3 TXD]]
|-
|-
| [[#CPU_GPIO_Table|CPU GPIO 0_9]]
| [[#GPIO|GPIO]]
| 91
| 91
!
!
| 92
| 92
| [[#UARTs|UART4 RXD]]
| [[#TS-8551_Mappings|UART3 RXD]]
|-
|-
| [[#Get_a_Console|DEBUG TXD]]
| [[#TS-8551_Mappings|DEBUG TXD]]
| 93
| 93
! C
! C
| 94
| 94
| [[#Crossbar|UARTC TXD]]
| [[#TS-8551_Mappings|UART4 TXD]]
|-
|-
| [[#Get_a_Console|DEBUG RXD]]
| [[#TS-8551_Mappings|DEBUG RXD]]
| 95
| 95
! N
! N
| 96
| 96
| [[#Crossbar|UARTC RXD]]
| [[#TS-8551_Mappings|UART4 RXD]]
|-
|-
| [[#CAN|CAN0 TXD]]
| [[#CAN|CAN TXD]]
| 97
| 97
! 2
! 2
| 98
| 98
| [[#Crossbar|UARTC TXD]]
| [[#TS-8551_Mappings|UART5 TXD]]
|-
|-
| [[#CAN|CAN0 RXD]]
| [[#CAN|CAN RXD]]
| 99
| 99
!
!
| 100
| 100
| [[#Crossbar|UARTC RXD]]
| [[#TS-8551_Mappings|UART5 RXD]]
|}
|}
|}
|}


<references />
<references />

Latest revision as of 17:33, 17 January 2022

The TS-SOCKET SoM devices all use 2 high density 100 pin connectors for power and all I/O. These follow a common pinout for various external interfaces so new modules can be switched in to an application in order to lower power consumption or use a more powerful processor. The male connector is on the baseboard, and the female connector is on the SoM. The datasheet for the baseboard's male connector can be found here. Connectors can be ordered from the SoM's product page as CN-TSSOCKET-M-10 for a 10 pack, or CN-TSSOCKET-M-100 for 100 pieces, or from the vendor of your choice; the part is an FCI 61083-102402LF.

TS-Socket

In our schematics and our table layout below, we refer to pin 1 from the male connector on the baseboard.


Example Baseboard


On the TS-8551, the entirety of both high-density connectors are broken out in to 0.1" spaced 2x25 pin headers. There are 4 of these in total, one each for CN1 odd numbered pins, CN1 even numbered pins, CN2 even numbered pins, and CN2 odd numbered pins. They are labeled on the silkscreen every 10 pins, with the first 2 and last 2 pins also being labeled.

Note that the below pinout is from the perspective of the TS-8551. However, the links for each pin will link to the relevant section in this manual. When designing a custom baseboard, it is advised to consider both the TS-8551's TS-SOCKET pinout and functions as well as the target SoM's pinout. For details on a specific SoM's interface, see that device's manual.

CN1 CN2
Name Pin Pin Name
FPGA_JTAG_TMS [1] 1 2 EXT_RESET# [2]
FPGA_JTAG_TCK [1] 3 C 4 EN_USB_5V [3]
FPGA_JTAG_TDO [1] 5 N 6 NC
FPGA_JTAG_TDI [1] 7 1 8 NC
OFF_BD_RESET# [4] 9 10 NC
Microcontroller C2 CLK [5] 11 12 NC
Microcontroller C2 DAT [5] 13 C 14 NC
5 V Power to SoM [6] 15 N 16 5 V Power to SoM [6]
No Charge Jumper / GPIO [7] 17 1 18 NC
U-Boot Jumper / GPIO [8] 19 20 NC
GPIO 21 22 FORCE_PWR_ON# [9]
GPIO 23 C 24 GPIO
GPIO 25 N 26 GPIO
GPIO 27 1 28 GPIO
5 V Power to SoM [6] 29 30 GPIO
GPIO 31 32 GPIO
GPIO 33 C 34 GPIO
GPIO 35 N 36 V_BAT
GPIO 37 1 38 GPIO
GPIO 39 40 GPIO
GPIO 41 42 GPIO
GPIO 43 C 44 GPIO
GPIO 45 N 46 GPIO
5 V Power to SoM [6] 47 1 48 GPIO
GPIO 49 50 USB_OTG_5V [10]
GPIO 51 52 BOOT_MODE_0 [11]
GPIO 53 C 54 NC
GPIO 55 N 56 NC
GPIO 57 1 58 GPIO
GPIO 59 60 GPIO
GPIO 61 62 Ground
GPIO 63 C 64 GPIO
GPIO 65 N 66 GPIO
RS-485 TX Enable / GPIO 67 1 68 GPIO
GPIO 69 70 GPIO
GPIO 71 72 GPIO
U-Boot Push Switch / GPIO 73 C 74 GPIO
Ground 75 N 76 GPIO
GPIO 77 1 78 GPIO
GPIO 79 80 GPIO
GPIO 81 82 GPIO
Board ID Data Out to SoM 83 C 84 GPIO
GPIO 85 N 86 GPIO
GPIO 87 1 88 GPIO
GPIO 89 90 GPIO
GPIO 91 92 GPIO
GPIO 93 C 94 GPIO
Ground 95 N 96 GPIO
GPIO 97 1 98 SD Boot Jumper [12] / GPIO
GPIO 99 100 GPIO
Name Pin Pin Name
Port 0 RX+ [13] / Port 0 BD_DA+ 1 2 Port 0 ACT_LED
Port 0 RX- [13] / Port 0 BD_DA- 3 C 4 Port 0 SPEED_LED
Port 0 CT 5 N 6 RED_LED#
Port 0 TX+ [13] / Port 0 BD_DB+ 7 2 8 GREEN_LED#
Port 0 TX- [13] / Port 0 BD_DB-+ 9 10 Port 1 ACT_LED
Port 0 CT 11 12 GPIO
3.3 VDC output from SoM 13 C 14 Ground
Ground 15 N 16 Port 1 RX+
Port 0 BD_DC+ 17 2 18 Port 1 RX-
Port 0 BD_DC- 19 20 Port 1 CT
Ground 21 22 Port 1 TX+
Port 0 BD_DD+ 23 C 24 Port 1 TX-
Port 0 BD_DD- 25 N 26 Ground
NC 27 2 28 I2C CLK
USB_HOST_M 29 30 I2C DAT
USB_HOST_P 31 32 GPIO
Ground 33 C 34 GPIO
USB_OTG_M 35 N 36 CPU_JTAG_TDI [14]
USB_OTG_P 37 2 38 CPU_JTAG_TDO [14]
3.3 VDC output from SoM 39 40 CPU_JTAG_TRST# [14]
SATA TX+ 41 42 CPU_JTAG_TCK [14]
SATA TX- 43 C 44 Ground
Ground 45 N 46 NC
SATA RX- 47 2 48 NC
SATA RX+ 49 50 Ground
Ground 51 52 GPIO
NC 53 C 54 CPU_JTAG_TMS [14]
NC 55 N 56 GPIO
SSD_PRESENT# 57 2 58 GPIO
NC 59 60 GPIO
NC 61 62 GPIO
1.8 VDC output from SoM [15] 63 C 64 GPIO
SPI CS# 65 N 66 GPIO
SPI MOSI 67 2 68 GPIO
SPI MISO 69 70 GPIO
SPI CLK 71 72 GPIO
Ground 73 C 74 USB_OTG_ID
SuperCap V+ 75 N 76 USB_OTG_5V [10]
SuperCap V+ 77 2 78 UART0 TXD [16]
3.3 VDC output from SoM 79 80 UART0 RXD [16]
SuperCap V+ 81 82 UART1 TXD [16]
SuperCap V+ 83 C 84 UART1 RXD [16]
Ground 85 N 86 UART2 TXD
SuperCap Junction 87 2 88 UART2 RXD
SuperCap Balance Drive 89 90 UART3 TXD
GPIO 91 92 UART3 RXD
DEBUG TXD 93 C 94 UART4 TXD
DEBUG RXD 95 N 96 UART4 RXD
CAN TXD 97 2 98 UART5 TXD
CAN RXD 99 100 UART5 RXD
  1. ↑ 1.0 1.1 1.2 1.3 The FPGA JTAG pins are not recommended for use and are not supported.
  2. ↑ EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain.
  3. ↑ This is an output which can be manipulated as a GPIO. This pin can optionally be connected to control a FET to a separate 5 V rail for USB to allow software to reset USB devices.
  4. ↑ OFF_BD_RESET# is an output from the SoM that automatically sends a reset signal when the unit powers up or reboots. It can be connected to any IC on the base board that requires a reset.
  5. ↑ 5.0 5.1 This interface is for programming the on-board microcontroller of the SoM, this should be left unconnected on a baseboard.
  6. ↑ 6.0 6.1 6.2 6.3 The power pins should each be provided with a 5 V source.
  7. ↑ Connect to a 1 kohm pull down to disable Supercapacitor charging on compatible SoMs. Can be used as GPIO after boot.
  8. ↑ Connect to a 1 kohm pull down to enter the U-Boot shell at power on on compatible SoMs. Can be used as GPIO after boot.
  9. ↑ When low, overrides the microcontroller power control and enables 5 V rail on the SoM. Leave unconnected for normal use.
  10. ↑ 10.0 10.1 Allows the supervisory microcontroller to measure USB VBUS for the OTG port.
  11. ↑ Normally NC or pulled to ground via 1 kohm resistor. Optionally can be switched/jumpered to pull to 3.3 V through a 1 kohm resistor; this allows other booting options provided by SoM. Not all SoMs honor this pin.
  12. ↑ Pull to ground through 1 kohm resistor to boot to SD. Leave floating to boot from on-board media. Do not connect directly to ground or 3.3 V or baseboard ID will no longer function.
  13. ↑ 13.0 13.1 13.2 13.3 The Ethernet jack on the TS-8551 is rated for 1000Base-T operation, but is compatible with 10/100Base-TX PHYs
  14. ↑ 14.0 14.1 14.2 14.3 14.4 The CPU JTAG pins are not recommended for use and are not supported.
  15. ↑ Not output from every SoM.
  16. ↑ 16.0 16.1 16.2 16.3 Do not connect to the TTL interface for this UART that is present on the CN breakout pin headers. Doing so may damage the SoM or the connected hardware
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