TS-8551-socket
The TS-SOCKET SoM devices all use 2 high density 100 pin connectors for power and all I/O. These follow a common pinout for various external interfaces so new modules can be switched in to an application in order to lower power consumption or use a more powerful processor. The male connector is on the baseboard, and the female connector is on the SoM. The datasheet for the baseboard's male connector can be found here. Connectors can be ordered from the SoM's product page as CN-TSSOCKET-M-10
for a 10 pack, or CN-TSSOCKET-M-100
for 100 pieces, or from the vendor of your choice; the part is an FCI 61083-102402LF
.
In our schematics and our table layout below, we refer to pin 1 from the male connector on the baseboard.
On the TS-8551, the entirety of both high-density connectors are broken out in to 0.1" spaced 2x25 pin headers. There are 4 of these in total, one each for CN1 odd numbered pins, CN1 even numbered pins, CN2 even numbered pins, and CN2 odd numbered pins. They are labeled on the silkscreen every 10 pins, with the first 2 and last 2 pins also being labeled.
- ↑ 1.0 1.1 1.2 1.3 The FPGA JTAG pins are not recommended for use and are not supported.
- ↑ EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain.
- ↑ This is an output which can be manipulated as a GPIO. This pin can optionally be connected to control a FET to a separate 5 V rail for USB to allow software to reset USB devices. Many of our baseboards implement this.
- ↑ OFF_BD_RESET# is an output from the SoM that automatically sends a reset signal when the unit powers up or reboots. It can be connected to any IC on the base board that requires a reset.
- ↑ 5.0 5.1 This interface is for programming the on-board microcontroller, this should be left unconnected on a baseboard.
- ↑ 6.0 6.1 6.2 6.3 The power pins should each be provided with a 5 V source.
- ↑ This is a multi-purpose pin, part of the FPGA Crossbar MUX. The CPU and FPGA pins are connected in parallel.
- ↑ When low, overrides the microcontroller power control and enables 5 V rail on the TS-4100. Leave unconnected for normal use.
- ↑ This is an output that can be manipulated as a GPIO.
- ↑ 10.0 10.1 Allows the supervisory microcontroller to measure USB VBUS for the OTG port.
- ↑ When held high during CPU startup, enables i.MX6UL USB Boot bootloader.
- ↑ 12.0 12.1 12.2 12.3 This pin is part of the FPGA Crossbar MUX. Its default Crossbar assignment is listed first, with the Crossbar name in parenthesis.