TS-8820-4700: Difference between revisions
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= Features = | = Features = | ||
== FPGA == | |||
The TS-8820 is powered by a Lattice XP2 FPGA with 5000 LUTs. Many but not all of the features listed in chapter 5 are driven by FPGA logic. The hardware functionality described in this document is programmed in the FPGA at the factory by default. The TS-SOCKET macrocontroller also has an FPGA, but when an FPGA is mentioned in this document it should be assumed that the TS-8820 FPGA is being discussed. | |||
The macrocontroller CoM communicates with the TS-8820 FPGA using the MUXBUS, a simple address/data bus defined by Technologic Systems and implemented in the macrocontroller FPGA. TS-8820 application developers do not need to understand the full hardware stack that enables TS-8820 registers to be accessed in memory space. It is necessary to program the MUXBUS registers with values that work for the TS-8820. The TS-8820 FPGA can handle very aggressive MUXBUS timing. See ts8820ctl source code for an example. | |||
For applications that require custom logic or interfaces, contact Technologic Systems regarding FPGA customization. | |||
== Non-Volatile RAM == | |||
The TS-8820 provides 2MB of battery backed static RAM. The RAM is accessed through a 4KB memory window. After programming the SRAM page register, 16 bit reads or writes can be performed to any part of the page. | |||
== Battery Socket == | |||
The coin cell battery is not required for TS-8820 operation. The battery provides backup power for the static RAM and for the real time clock (on the macrocontroller). Without a battery, a loss of power will result in a loss of RTC time and SRAM data. | |||
== PWM == | == PWM == | ||
PWMs 1 to 6 feed digital outputs 1 to 6, respectively, only if the PWM override bit is set for the output in question. PWMs 7 and 8 are used for H-bridges. If an H-bridge is not enabled, both contacts will be high impedance. If it is enabled, it will have one side tied to ground and the other side driven by the PWM. The direction bit can be toggled at any time to toggle the H-bridge direction. "Brake mode" with both sides high is not supported by the current FPGA version. | PWMs 1 to 6 feed digital outputs 1 to 6, respectively, only if the PWM override bit is set for the output in question. PWMs 7 and 8 are used for H-bridges. If an H-bridge is not enabled, both contacts will be high impedance. If it is enabled, it will have one side tied to ground and the other side driven by the PWM. The direction bit can be toggled at any time to toggle the H-bridge direction. "Brake mode" with both sides high is not supported by the current FPGA version. | ||
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When 0 is written to the control bit, the DAC values are updated internally in the FPGA but not transferred to the DAC. Thus any set of channels can be updated simultaneously by only writing a one on the final write. | When 0 is written to the control bit, the DAC values are updated internally in the FPGA but not transferred to the DAC. Thus any set of channels can be updated simultaneously by only writing a one on the final write. | ||
== Isolated Inputs == | |||
Each isolated input has a positive and negative terminal. In order to activate the input, a potential of at least 3V and not more than 30V must be generated across these terminals. Isolated input terminals are on [[#Terminal Blocks|P1 and P3]]. | |||
== Isolated Outputs == | |||
The 4 isolated outputs each have a positive and negative terminal. Each output acts as a passive switch, allowing current to flow only when it is activated. Isolated output terminals are on [[#Terminal Blocks|P3]]. | |||
== Non-Isolated Outputs == | |||
Outputs 5 and 6 are non-isolated and appear on [[#Terminal Blocks|P9]]. When set low, they can sink 1000mA. | |||
== Buffered Inputs == | |||
Digital inputs 9 to 14 are buffered but not isolated. They have a nominal threshold of 2.5V and a 3.24K pull-up to 5V. These inputs are 40V tolerant. They are on terminal block [[#Terminal Blocks|P9]]. | |||
== ADC Channels == | |||
The 16 ADC channels are on [[#Terminal Blocks|P4, P6, and P5]]. Inputs for these channels must be in the -10V to +10V range. It is also possible to select a -5V to +5V range in software. On [[#Terminal Blocks|P4, P6, and P5]], all even numbered terminals are connected to ground. Odd numbered terminals are used for ADC inputs and DAC outputs. | |||
== DAC Channels == | |||
Each DAC channel produces an output voltage in the 0 to +10V range. DAC terminals are on [[#Terminal Blocks|P5 and P10]]. Even numbered terminals next to DAC terminals are connected to ground. | |||
== H-Bridges == | |||
The TS-8820 supports 2 H-bridges on terminal block [[#Terminal Blocks|P2]]. One bridge drives terminals 1 and 2, and the second drives terminals 3 and 4. Each pair of terminals can be connected directly to a DC motor. Each H-bridge can supply up to 2.8A of current. | |||
== Isolated CAN Port == | |||
An isolated CAN port is available on [[#Terminal Blocks|P8]]. CAN high and low lines are on terminals 11 and 12, respectively. The common CAN ground is on terminal 10. | |||
== Isolated RS-232 == | |||
An isolated RS-232 port is on [[#Terminal Blocks|P8]], with TX on terminal 7 and RX on terminal 8. The RS-232 port is driven by macrocontroller UART 1. | |||
== Isolated RS-485 == | |||
An isolated RS-485 port is on [[#Terminal Blocks|P8]]. Terminals 5 and 6 are the + and - lines, respectively. The RS-485 port is driven by macrocontroller UART 0. | |||
== Relays == | |||
Terminal block [[#Terminal Blocks|P7]] is connected to 4 SPDT relays. Each relay has a COM line which is always connected to either the NC line (relay not activated) or the NO line (relay activated). Relays 1 to 4 are activated by macrocontroller DIO 8, 7, 6, and 4, respectively. | |||
== Power Supply == | |||
If PoE is not used, power must be supplied on terminal block P2. Supply an external ground on terminal 10, 11, and/or 12. Supply +10V to +30V on terminal 7, 8, and/or 9. | |||
== LEDS == | == LEDS == | ||
Line 71: | Line 120: | ||
|- | |- | ||
| 1 | | 1 | ||
| IN1+ | | [[#Isolated Inputs|IN1+]] | ||
|- | |- | ||
| 2 | | 2 | ||
| IN1- | | [[#Isolated Inputs|IN1-]] | ||
|- | |- | ||
| 3 | | 3 | ||
| IN2+ | | [[#Isolated Inputs|IN2+]] | ||
|- | |- | ||
| 4 | | 4 | ||
| IN2- | | [[#Isolated Inputs|IN2-]] | ||
|- | |- | ||
| 5 | | 5 | ||
| IN3+ | | [[#Isolated Inputs|IN3+]] | ||
|- | |- | ||
| 6 | | 6 | ||
| IN3- | | [[#Isolated Inputs|IN3-]] | ||
|- | |- | ||
| 7 | | 7 | ||
| IN4+ | | [[#Isolated Inputs|IN4+]] | ||
|- | |- | ||
| 8 | | 8 | ||
| IN4- | | [[#Isolated Inputs|IN4-]] | ||
|- | |- | ||
| 9 | | 9 | ||
| IN5+ | | [[#Isolated Inputs|IN5+]] | ||
|- | |- | ||
| 10 | | 10 | ||
| IN5- | | [[#Isolated Inputs|IN5-]] | ||
|- | |- | ||
| 11 | | 11 | ||
| IN6+ | | [[#Isolated Inputs|IN6+]] | ||
|- | |- | ||
| 12 | | 12 | ||
| IN6- | | [[#Isolated Inputs|IN6-]] | ||
|} | |} | ||
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|- | |- | ||
| 7 | | 7 | ||
| EXT_12V_24V | | [[#Power Supply|EXT_12V_24V]] | ||
|- | |- | ||
| 8 | | 8 | ||
| EXT_12V_24V | | [[#Power Supply|EXT_12V_24V]] | ||
|- | |- | ||
| 9 | | 9 | ||
| EXT_12V_24V | | [[#Power Supply|EXT_12V_24V]] | ||
|- | |- | ||
| 10 | | 10 | ||
| EXT_POWER_RET | | [[#Power Supply|EXT_POWER_RET]] | ||
|- | |- | ||
| 11 | | 11 | ||
| EXT_POWER_RET | | [[#Power Supply|EXT_POWER_RET]] | ||
|- | |- | ||
| 12 | | 12 | ||
| EXT_POWER_RET | | [[#Power Supply|EXT_POWER_RET]] | ||
|} | |} | ||
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|- | |- | ||
| 1 | | 1 | ||
| IN7+ | | [[#Isolated Inputs|IN7+]] | ||
|- | |- | ||
| 2 | | 2 | ||
| IN7- | | [[#Isolated Inputs|IN7-]] | ||
|- | |- | ||
| 3 | | 3 | ||
| IN8+ | | [[#Isolated Inputs|IN8+]] | ||
|- | |- | ||
| 4 | | 4 | ||
| IN8- | | [[#Isolated Inputs|IN8-]] | ||
|- | |- | ||
| 5 | | 5 | ||
| OUT1+ | | [[#Isolated Outputs|OUT1+]] | ||
|- | |- | ||
| 6 | | 6 | ||
| OUT1- | | [[#Isolated Outputs|OUT1-]] | ||
|- | |- | ||
| 7 | | 7 | ||
| OUT2+ | | [[#Isolated Outputs|OUT2+]] | ||
|- | |- | ||
| 8 | | 8 | ||
| OUT2- | | [[#Isolated Outputs|OUT2-]] | ||
|- | |- | ||
| 9 | | 9 | ||
| OUT3+ | | [[#Isolated Outputs|OUT3+]] | ||
|- | |- | ||
| 10 | | 10 | ||
| OUT3- | | [[#Isolated Outputs|OUT3-]] | ||
|- | |- | ||
| 11 | | 11 | ||
| OUT4+ | | [[#Isolated Outputs|OUT4+]] | ||
|- | |- | ||
| 12 | | 12 | ||
| OUT4- | | [[#Isolated Outputs|OUT4-]] | ||
|} | |} | ||
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|- | |- | ||
| 1 | | 1 | ||
| ADC Channel 1 | | [[#ADC Channels|ADC Channel 1]] | ||
|- | |- | ||
| 2 | | 2 | ||
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|- | |- | ||
| 3 | | 3 | ||
| ADC Channel 2 | | [[#ADC Channels|ADC Channel 2]] | ||
|- | |- | ||
| 4 | | 4 | ||
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|- | |- | ||
| 5 | | 5 | ||
| ADC Channel 3 | | [[#ADC Channels|ADC Channel 3]] | ||
|- | |- | ||
| 6 | | 6 | ||
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|- | |- | ||
| 7 | | 7 | ||
| ADC Channel 4 | | [[#ADC Channels|ADC Channel 4]] | ||
|- | |- | ||
| 8 | | 8 | ||
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|- | |- | ||
| 9 | | 9 | ||
| ADC Channel 5 | | [[#ADC Channels|ADC Channel 5]] | ||
|- | |- | ||
| 10 | | 10 | ||
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|- | |- | ||
| 11 | | 11 | ||
| ADC Channel 6 | | [[#ADC Channels|ADC Channel 6]] | ||
|- | |- | ||
| 12 | | 12 | ||
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|- | |- | ||
| 1 | | 1 | ||
| ADC Channel 13 | | [[#ADC Channels|ADC Channel 13]] | ||
|- | |- | ||
| 2 | | 2 | ||
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|- | |- | ||
| 3 | | 3 | ||
| ADC Channel 14 | | [[#ADC Channels|ADC Channel 14]] | ||
|- | |- | ||
| 4 | | 4 | ||
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|- | |- | ||
| 5 | | 5 | ||
| ADC Channel 15 | | [[#ADC Channels|ADC Channel 15]] | ||
|- | |- | ||
| 6 | | 6 | ||
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|- | |- | ||
| 7 | | 7 | ||
| ADC Channel 16 | | [[#ADC Channels|ADC Channel 16]] | ||
|- | |- | ||
| 8 | | 8 | ||
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|- | |- | ||
| 9 | | 9 | ||
| DAC 1 | | [[#DAC Channels|DAC 1]] | ||
|- | |- | ||
| 10 | | 10 | ||
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|- | |- | ||
| 11 | | 11 | ||
| DAC 2 | | [[#DAC Channels|DAC 2]] | ||
|- | |- | ||
| 12 | | 12 | ||
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|- | |- | ||
| 1 | | 1 | ||
| ADC Channel 7 | | [[#ADC Channels|ADC Channel 7]] | ||
|- | |- | ||
| 2 | | 2 | ||
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|- | |- | ||
| 3 | | 3 | ||
| ADC Channel 8 | | [[#ADC Channels|ADC Channel 8]] | ||
|- | |- | ||
| 4 | | 4 | ||
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|- | |- | ||
| 5 | | 5 | ||
| ADC Channel 9 | | [[#ADC Channels|ADC Channel 9]] | ||
|- | |- | ||
| 6 | | 6 | ||
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|- | |- | ||
| 7 | | 7 | ||
| ADC Channel 10 | | [[#ADC Channels|ADC Channel 10]] | ||
|- | |- | ||
| 8 | | 8 | ||
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|- | |- | ||
| 9 | | 9 | ||
| ADC Channel 11 | | [[#ADC Channels|ADC Channel 11]] | ||
|- | |- | ||
| 10 | | 10 | ||
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|- | |- | ||
| 11 | | 11 | ||
| ADC Channel 12 | | [[#ADC Channels|ADC Channel 12]] | ||
|- | |- | ||
| 12 | | 12 | ||
Line 342: | Line 391: | ||
|- | |- | ||
| 1 | | 1 | ||
| Relay 1 NO | | [[#Relays|Relay 1 NO]] | ||
|- | |- | ||
| 2 | | 2 | ||
| Relay 1 COM | | [[#Relays|Relay 1 COM]] | ||
|- | |- | ||
| 3 | | 3 | ||
| Relay 1 NC | | [[#Relays|Relay 1 NC]] | ||
|- | |- | ||
| 4 | | 4 | ||
| Relay 2 NO | | [[#Relays|Relay 2 NO]] | ||
|- | |- | ||
| 5 | | 5 | ||
| Relay 2 COM | | [[#Relays|Relay 2 COM]] | ||
|- | |- | ||
| 6 | | 6 | ||
| Relay 2 NC | | [[#Relays|Relay 2 NC]] | ||
|- | |- | ||
| 7 | | 7 | ||
| Relay 3 NO | | [[#Relays|Relay 3 NO]] | ||
|- | |- | ||
| 8 | | 8 | ||
| Relay 3 COM | | [[#Relays|Relay 3 COM]] | ||
|- | |- | ||
| 9 | | 9 | ||
| Relay 3 NC | | [[#Relays|Relay 3 NC]] | ||
|- | |- | ||
| 10 | | 10 | ||
| Relay 3 NO | | [[#Relays|Relay 3 NO]] | ||
|- | |- | ||
| 11 | | 11 | ||
| Relay 3 COM | | [[#Relays|Relay 3 COM]] | ||
|- | |- | ||
| 12 | | 12 | ||
| Relay 3 NC | | [[#Relays|Relay 3 NC]] | ||
|} | |} | ||
Line 433: | Line 482: | ||
|- | |- | ||
| 1 | | 1 | ||
| IN 9 | | [[#Buffered Inputs|IN 9]] | ||
|- | |- | ||
| 2 | | 2 | ||
| IN 10 | | [[#Buffered Inputs|IN 10]] | ||
|- | |- | ||
| 3 | | 3 | ||
Line 442: | Line 491: | ||
|- | |- | ||
| 4 | | 4 | ||
| IN 11 | | [[#Buffered Inputs|IN 11]] | ||
|- | |- | ||
| 5 | | 5 | ||
| IN 12 | | [[#Buffered Inputs|IN 12]] | ||
|- | |- | ||
| 6 | | 6 | ||
Line 451: | Line 500: | ||
|- | |- | ||
| 7 | | 7 | ||
| IN 13 | | [[#Buffered Inputs|IN 13]] | ||
|- | |- | ||
| 8 | | 8 | ||
| IN 14 | | [[#Buffered Inputs|IN 14]] | ||
|- | |- | ||
| 9 | | 9 | ||
Line 460: | Line 509: | ||
|- | |- | ||
| 10 | | 10 | ||
| OUT 5 | | [[#Non-Isolated Outputs|OUT 5]] | ||
|- | |- | ||
| 11 | | 11 | ||
| OUT 6 | | [[#Non-Isolated Outputs|OUT 6]] | ||
|- | |- | ||
| 12 | | 12 | ||
Line 478: | Line 527: | ||
|- | |- | ||
| 1 | | 1 | ||
| DAC 3 | | [[#DAC Channels|DAC 3]] | ||
|- | |- | ||
| 2 | | 2 | ||
Line 484: | Line 533: | ||
|- | |- | ||
| 3 | | 3 | ||
| DAC 4 | | [[#DAC Channels|DAC 4]] | ||
|- | |- | ||
| 4 | | 4 | ||
Line 515: | Line 564: | ||
|} | |} | ||
== Ethernet Connector == | |||
The TS-8820 can connect to any Ethernet LAN. Ethernet is fully supported by any TS-SOCKET macrocontroller. The Ethernet connector includes LEDs indicating link and activity. The link LED should be on whenever the TS-8820 is powered and connected to a LAN. This connector allows the TS-8820 to be powered by PoE. | |||
== USB Host == | == USB Host == |
Revision as of 21:02, 26 March 2012
Product Page | |
Image Gallery |
Overview
The TS-8820-BOX is a rugged, feature-rich TS-SOCKET based baseboard and Macrocontroller combination for industrial applications. Powered by either the TS-4700 or TS-4800 Macrocontroller Computer on Module, the TS-8820-BOX provides a variety of electrically isolated I/O.. The TS-8820-BOX enclosure exposes the I/O on rugged screw terminals while protecting the macrocontroller and other sensitive electronics. The TS-8820-BOX with an 800MHz TS-4700 or TS-4800 in the aluminum enclosure provides a tough, durable, flexible, powerful, and affordable industrial process control system platform.
TS-4700
See the TS-4700 page for functionality regarding the CPU, FPGA, and OS.
Marvell PXA166 800MHz ARM9 |
Getting Started
- Place the TS-8820 base board on a firm non-conductive surface.
- Carefully, insert the TS-4000 Series Macrocontroller by aligning and pressing evenly and firmly onto the pair of mating connectors
- Connect the console serial terminal cable
- Connect the Ethernet cable if applicable.
- Connect the GND and POWER screw terminals to a voltage source from 10V to 30V DC.
- Alternatively, the board can be powered through POE
- Apply power
- Monitor the TS-SOCKET SBC using a terminal emulator connected to the serial console port to verify that the board is operating properly
See the TS-4700 page for more details on dealing with the functionality of the macrocontroller.
Features
FPGA
The TS-8820 is powered by a Lattice XP2 FPGA with 5000 LUTs. Many but not all of the features listed in chapter 5 are driven by FPGA logic. The hardware functionality described in this document is programmed in the FPGA at the factory by default. The TS-SOCKET macrocontroller also has an FPGA, but when an FPGA is mentioned in this document it should be assumed that the TS-8820 FPGA is being discussed.
The macrocontroller CoM communicates with the TS-8820 FPGA using the MUXBUS, a simple address/data bus defined by Technologic Systems and implemented in the macrocontroller FPGA. TS-8820 application developers do not need to understand the full hardware stack that enables TS-8820 registers to be accessed in memory space. It is necessary to program the MUXBUS registers with values that work for the TS-8820. The TS-8820 FPGA can handle very aggressive MUXBUS timing. See ts8820ctl source code for an example.
For applications that require custom logic or interfaces, contact Technologic Systems regarding FPGA customization.
Non-Volatile RAM
The TS-8820 provides 2MB of battery backed static RAM. The RAM is accessed through a 4KB memory window. After programming the SRAM page register, 16 bit reads or writes can be performed to any part of the page.
Battery Socket
The coin cell battery is not required for TS-8820 operation. The battery provides backup power for the static RAM and for the real time clock (on the macrocontroller). Without a battery, a loss of power will result in a loss of RTC time and SRAM data.
PWM
PWMs 1 to 6 feed digital outputs 1 to 6, respectively, only if the PWM override bit is set for the output in question. PWMs 7 and 8 are used for H-bridges. If an H-bridge is not enabled, both contacts will be high impedance. If it is enabled, it will have one side tied to ground and the other side driven by the PWM. The direction bit can be toggled at any time to toggle the H-bridge direction. "Brake mode" with both sides high is not supported by the current FPGA version.
For all 8 PWMs, the PWM frequency is approximately 12207/(2^prescalar). PWM duty cycle has 12 bits of resolution. If bit 13 is set, the output will be 100% high. Otherwise, the duty cycle setting is divided by 4096 to give the effective duty cycle.
DAC
DAC output registers have 12 data bits (bits 11:0) and one control bit (bit 15). Bits 14:12 are reserved. The control bit is used for synchronization of output voltage updates across multiple channels if necessary and for ensuring software compliance with hardware requirements. When a 1 is written to the control bit, DAC data is sent to all channels even if it has not been changed since the last update. After an update is initiated, software can read the control bit to see if the system is still busy. Further writes of DAC values while the hardware is busy will result in undefined behavior. The update process takes approximately 3 microseconds.
When 0 is written to the control bit, the DAC values are updated internally in the FPGA but not transferred to the DAC. Thus any set of channels can be updated simultaneously by only writing a one on the final write.
Isolated Inputs
Each isolated input has a positive and negative terminal. In order to activate the input, a potential of at least 3V and not more than 30V must be generated across these terminals. Isolated input terminals are on P1 and P3.
Isolated Outputs
The 4 isolated outputs each have a positive and negative terminal. Each output acts as a passive switch, allowing current to flow only when it is activated. Isolated output terminals are on P3.
Non-Isolated Outputs
Outputs 5 and 6 are non-isolated and appear on P9. When set low, they can sink 1000mA.
Buffered Inputs
Digital inputs 9 to 14 are buffered but not isolated. They have a nominal threshold of 2.5V and a 3.24K pull-up to 5V. These inputs are 40V tolerant. They are on terminal block P9.
ADC Channels
The 16 ADC channels are on P4, P6, and P5. Inputs for these channels must be in the -10V to +10V range. It is also possible to select a -5V to +5V range in software. On P4, P6, and P5, all even numbered terminals are connected to ground. Odd numbered terminals are used for ADC inputs and DAC outputs.
DAC Channels
Each DAC channel produces an output voltage in the 0 to +10V range. DAC terminals are on P5 and P10. Even numbered terminals next to DAC terminals are connected to ground.
H-Bridges
The TS-8820 supports 2 H-bridges on terminal block P2. One bridge drives terminals 1 and 2, and the second drives terminals 3 and 4. Each pair of terminals can be connected directly to a DC motor. Each H-bridge can supply up to 2.8A of current.
Isolated CAN Port
An isolated CAN port is available on P8. CAN high and low lines are on terminals 11 and 12, respectively. The common CAN ground is on terminal 10.
Isolated RS-232
An isolated RS-232 port is on P8, with TX on terminal 7 and RX on terminal 8. The RS-232 port is driven by macrocontroller UART 1.
Isolated RS-485
An isolated RS-485 port is on P8. Terminals 5 and 6 are the + and - lines, respectively. The RS-485 port is driven by macrocontroller UART 0.
Relays
Terminal block P7 is connected to 4 SPDT relays. Each relay has a COM line which is always connected to either the NC line (relay not activated) or the NO line (relay activated). Relays 1 to 4 are activated by macrocontroller DIO 8, 7, 6, and 4, respectively.
Power Supply
If PoE is not used, power must be supplied on terminal block P2. Supply an external ground on terminal 10, 11, and/or 12. Supply +10V to +30V on terminal 7, 8, and/or 9.
LEDS
The TS-8820 has 27 LED indicators. Most are used to provide instant visual confirmation of the states of DIO and relays. Each LED is labeled on the silkscreen.
LED5 to LED8 indicate relay 1 to relay 4 are activated, respectively.
LED9 to LED16 correspond with digital inputs 1 to 8.
LED17 to LED20 correspond with digital outputs 1 to 4.
LED21 to LED26 correspond with digital inputs 9 to 14.
LED27 and LED28 correspond with digital outputs 5 and 6.
LED3 indicates power is supplied to the TS-8820. LED1 and LED4 are connected to the standard red and green LED lines used on most TS-SOCKET systems.
Connectors
Terminal Blocks
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Ethernet Connector
The TS-8820 can connect to any Ethernet LAN. Ethernet is fully supported by any TS-SOCKET macrocontroller. The Ethernet connector includes LEDs indicating link and activity. The link LED should be on whenever the TS-8820 is powered and connected to a LAN. This connector allows the TS-8820 to be powered by PoE.
USB Host
The USB is available on two ports as a USB 2.0 host.
|
DB9 Connector
class=wikitable | |
Pin | Description |
---|---|
1 | XUART4 RS485+ |
2 | Debug Console RS232 RXD |
3 | Debug Console RS232 TXD |
4 | Not Connected |
5 | Ground |
6 | XUART4 RS485- |
7 | XUART2 RS232 TXD |
8 | XUART2 RS232 RXD |
9 | Not Connected |
Register Map
Most of the access to the IO should be abstracted by ts8820ctl and ts8820.c, but you can also access these IO directly through the MUXBUS registers.
Offset | Bits | Description |
---|---|---|
0x0 | 15:0 | Model ID: Reads 0x8820 |
0x2 | 15:8 | Reserved |
7 | H-bridge 2 enable (contacts go high-Z otherwise) | |
6 | H-bridge 1 enable (contacts go high-Z otherwise) | |
5 | H-bridge 2 direction | |
4 | H-bridge 1 direction | |
3:0 | FPGA Revision | |
0x4 | 15:14 | Reserved |
13:0 | Digital inputs 14:1 | |
0x6 | 15:10 | Reserved |
9:0 | SRAM Page register | |
0x8 | 15:12 | Reserved |
11:6 | Override Digital Outputs 6:1 with PWM | |
5:0 | Digital Output Values 6:1 | |
0xa | 15:0 | Reserved |
0xc | 15:0 | Reserved |
0xe | 15:0 | Reserved |
0x10 | 15:13 | PWM #1 Prescaler |
12:0 | PWM #1 Duty Cycle | |
0x12 | 15:13 | PWM #2 Prescalar |
12:0 | PWM #2 Duty Cycle | |
0x14 | 15:13 | PWM #3 Prescaler |
12:0 | PWM #3 Duty Cycle | |
0x16 | 15:13 | PWM #4 Prescaler |
12:0 | PWM #4 Duty Cycle | |
0x18 | 15:13 | PWM #5 Prescaler |
12:0 | PWM #5 Duty Cycle | |
0x1a | 15:13 | PWM #6 Prescaler |
12:0 | PWM #6 Duty Cycle | |
0x1c | 15:13 | PWM #7 Prescaler |
12:0 | PWM #7 Duty Cycle | |
0x1e | 15:13 | PWM #8 Prescaler |
12:0 | PWM #8 Duty Cycle | |
0x20 | 15:0 | Pulse Counter #1 |
0x22 | 15:0 | Pulse Counter #2 |
0x24 | 15:0 | Pulse Counter #3 |
0x26 | 15:0 | Pulse Counter #4 |
0x28 | 15:0 | Pulse Counter #5 |
0x2a | 15:0 | Pulse Counter #6 |
0x2c | 15:0 | Pulse Counter #7 |
0x2e | 15:0 | Pulse Counter #8 |
0x30 | 15:0 | Pulse Counter #9 |
0x32 | 15:0 | Pulse Counter #10 |
0x34 | 15:0 | Pulse Counter #11 |
0x36 | 15:0 | Pulse Counter #12 |
0x38 | 15:0 | Pulse Counter #13 |
0x3a | 15:0 | Pulse Counter #14 |
0x3c | 15:0 | Reserved |
0x3e | 15:0 | Reserved |
0x80 | 15:0 | ADC Core ID (reads 0xadc1) |
0x82 | 15:8 | ADC Channel Mask (0 = do not save channel data) |
7:6 | Highest number chip to use (0-3) | |
5 | 1 = Force standby | |
4 | 1 = Use standby between samples to save power | |
3 | 1 = Smart DMA IRQ mode | |
2 | 1 = Enable IRQ | |
1 | 1 = Collect samples, 0 = stop | |
0 | 1 = Reset ADC chips and all FIFOs | |
0x84 | 15 | 1 = There has been a FIFO overflow since last reset |
14:0 | Number of samples available to be read | |
0x86 | 15:0 | Sample Data (RO) |
0x88 | 15:0 | Sampling period LSB (RW) |
0x8a | 15:0 | Sampling period MSB (RW) |
0x8c | 15:0 | IRQ Threshold (RW) |
0x8e | 15:0 | DMA transfer size for smart mode (RW) (TODO) |
0x90 | 15:0 | Reserved |
0x92 | 15:0 | Reserved |
0x94 | 15:0 | Reserved |
0x96 | 15:0 | Reserved |
0x98 | 15:0 | Reserved |
0x9a | 15:0 | Reserved |
0x9c | 15:0 | Reserved |
0x9e | 15:0 | Reserved |
0xa0 | 15:0 | DAC 1 Control Register |
0xa2 | 15:0 | DAC 2 Control Register |
0xa4 | 15:0 | DAC 3 Control Register |
0xa6 | 15:0 | DAC 4 Control Register |