TS-9700

TS-9700

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Schematic

Overview

The Technologic Systems TS-9700 is a PC/104 daughter board that provides 8 channels of 12-bit Analog-to-Digital (A/D) conversion using a precision 0.2% analog reference. A single Analog Devices AD7888 chip implements the heart of the A/D subsystem. Each analog input can be individually jumper selected for one of three ranges:

 0 – 2.5 Volt 
 0 – 10.0 Volt 
 0 – 20 mA 

The Analog-to-Digital conversion takes 9 microseconds to complete allowing up to 100K samples per second. The TS-9700 can optionally be populated with 4 channels of 12-bit digital-to-analog conversion using a 0.2% analog reference. Two Texas Instruments TLV5818 chips are used to implement the four Digital-to-Analog converter (DAC) outputs. Each DAC output has a rail-to-rail output buffer that allows a nominal 0 to 5 Volt output swing using a single 5V power supply.

PC104 Interface

The TS-9700 features an 8-bit industry standard PC/104 bus that is compatible with all Technologic Systems series of SBC. The TS-9700 requires a block of 8 bytes in the I/O space. The location of the base I/O address of this block can be selected via 3 jumpers as shown in Table 1 This allows for multiple TS-9700 boards to be used in a single system. A Xilinx programmable logic device (PLD) is used to decode the Base I/O address. This allows for a great amount of flexibility in the standard product and allows for custom configurations if they are necessary. Call Technologic Systems for more details.

IO Address

JP1	JP2	JP3	IO Address
Off	Off	Off	0x160
On	Off	Off	0x168
Off	On	Off	0x180
On	On	Off	0x188
Off	Off	On	0x250
On	Off	On	0x258
Off	On	On	0x268
On	On	On	0x268

Register Map

Any write to the A/D command register at offset 0x0 will initiate an analog-to-digital conversion with the 12-bit result being stored into the A/D LSB and A/D MSB registers. Bits 0-2 select the channel (0-7) to be converted. The result will not be available for approximately 9 microseconds (for single acquisition mode) after the command register has been written. This delay is due to the acquisition time required by the AD7888 chip. The 12-bit result can be read in a single 16-bit word cycle or as two byte reads. Since there are only 12-bits for each acquisition, the upper 4-bits of the A/D MSB register are always read as zeros. The A/D command register should be polled (read cycles only) until bit 7 is set high before attempting to read the A/D result. Bit 7 of the A/D command register is a read-only status bit that is a logic 0 while an A/D acquisition is in progress.

The TS-9700 allows two different types of acquisitions, single cycle and double cycle modes. The single cycle mode (Bit 4 = logic 1) takes 9 microseconds to complete while a double cycle requires 18 microseconds. Due to the design of the AD7888 chip, it is not possible to select the channel to convert and also convert the selected channel in a single 9 microsecond cycle. The AD7888 uses a pipelined architecture where the channel being converted is determined by the value of bits 0-2 for the previous cycle. This mode can be used for the highest sampling rate possible, but if you need to sample random channels, it is simpler to use the double cycle mode (Bit 4 = logic 0). In the double cycle mode, the Xilinx PLD state machine does two complete acquisitions, with the first used to get the desired channel into the AD7888 chip, and the second cycle then does the acquisition on the correct channel.

Offset	Bits	Description	Access
0x0	7	Read/Write	A/D Acquisition Status (ready = 1)
	5:6	Read/Only	Reserved
	4	Read/Write	Single Acquisition Mode (single = 1)
	3	Read Only	Reserved
	0:2	Selects A/D channel	Read/Write
0x1	7-0	Read/Write	ID Register (0x97)
0x2	7:0	Read/Only	A/D LSB
0x3	7:0	Read/Only	A/D MSB (upper 4 bits = 0)
0x4	7:0	Read/Write	Value to DAC
0x5	8:7	Read/Write	DAC Select 00 = Channel #1 01 = Channel #2 10 = Channel #3 11 = Channel #4
	6	Read/Write	Write to buffer only
	5	Read/Write	Fast DAC mode
	4:0	Read/Write	Value to DAC
0x6	7:0	Read Only	DAC Status (bit 7 = Ready)
0x7	7:0	Read Only	Reserved

Product Notes

FCC Advisory

This equipment generates, uses, and can radiate radio frequency energy and if not installed and used properly (that is, in strict accordance with the manufacturer's instructions), may cause interference to radio and television reception. It has been type tested and found to comply with the limits for a Class A digital device in accordance with the specifications in Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment. Operation of this equipment in a residential area is likely to cause interference, in which case the owner will be required to correct the interference at his own expense.

If this equipment does cause interference, which can be determined by turning the unit on and off, the user is encouraged to try the following measures to correct the interference:

Reorient the receiving antenna. Relocate the unit with respect to the receiver. Plug the unit into a different outlet so that the unit and receiver are on different branch circuits. Ensure that mounting screws and connector attachment screws are tightly secured. Ensure that good quality, shielded, and grounded cables are used for all data communications. If necessary, the user should consult the dealer or an experienced radio/television technician for additional suggestions. The following booklets prepared by the Federal Communications Commission (FCC) may also prove helpful:

How to Identify and Resolve Radio-TV Interference Problems (Stock No. 004-000-000345-4) Interface Handbook (Stock No. 004-000-004505-7) These booklets may be purchased from the Superintendent of Documents, U.S. Government Printing Office, Washington, DC 20402.

Limited Warranty

See our Terms and Conditions for more details.