TS-ADC16

TS-ADC16

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ADC Datasheet
DAC Datasheet

Overview

The TS-ADC16 is a 8-bit (16-bit in ARM mode) PC/104 peripheral board that provides 16 channels of 16-bit analog to digital conversion at 2x1ksps sample rate, 4 channels of 12-bit digital to analog conversion, 4 digital inputs, 4 16-bit edge counters, and 1 digital output. This PC/104 peripheral will work with nearly all PC/104 masters in 8-bit mode, and is compatible with Technologic Systems' PC/104 SBCs in 16-bit or 8-bit mode.

Features

Analog to Digital conversion

Voltage range is selected for the entire 16 ADC channels, selectable ranges are:

 -5v to 5v single or differential
 0v to 5v single or differential
 -10v to 10v single or differential
 0v to 10v single or differential

During acquisition, two channels are sampled simultaneously (one from each of the two ADC chips) and stored in channel number order to the ADC FIFO. The number of pairs of channels to be converted is configurable. The TS-ADC16 has a variable sample rate, going as high as 1ksps; a single sample is one channel from each of the two ADC chips simultaneously. The ADC conversion state machine can be started by setting the ADCCFG register or via a negative edge trigger on digital input 0. Once the ADC conversion state machine is started, it can be stopped by clearing the SYSCOM bit, or it will automatically stop if the ADC FIFO fills up.

Interrupt capable FIFO

The TS-ADC16 has internal 512x16-bit FIFO built in to the on-board PLD. The FIFO is capable of generating interrupts on the PC/104 bus which are fired at a user-selectable FIFO count level; this defaults to half-full.

Counters

There are 4 16-bit counters built in to the TS-ADC16. These are negative edge triggered and permanently tied to their respectively numbered digital input pins. During a read, the current counter value is latched in at the read strobe assertion. The counters are not clearable, and will loop back to 0x0 after 0xffff.

Digital to Analog conversion

The TS-ADC16 has 4 DAC outputs, each with independent gain and a maximum drive strength of 25mA. The selectable gains are:

 0v to 2.5v
 0v to 5v

Digital Inputs

There are 4 buffered digital inputs available on the TS-ADC16. These are fed in to the Counters, and digital input 0 can be used as a trigger to start the ADC conversion state machine. All 4 digital inputs are 5v tolerant.

Digital Output

There is 1 digital output on the TS-ADC16. It outputs 0 and 3.3v, and can sink/source 50mA.

Analog to Digital converter

The TS-ADC16 uses two LTC1859 ADC chips to provide two sets of 8, 16-bit ADC channels. Each of the two chips is fed the same SPI packet for each conversion. This means that channels are acquired in pairs (one channel from each chip) for each sample conversion; also voltage range, sample speed, and sample mode are applied to both chips and therefore all of the ADC input channels all have the same configuration. Each of the 16 channels has a 42kΩ input impedance in unipolar mode (0v to Xv), and 31kΩ input impedance in bipolar mode (-Xv to Xv). See the LTC1859 Datasheet for more detailed information about the ADC inputs.

Operation

The ADC conversion state machine is started by setting SYSCOM or having digital input 0 go low with EXTTRIG set. As soon as this happens, the contents of ADCCFG are latched in and samples are acquired. The ADC conversion state machine will sample from channel pair 0 to NUMCHAN set in ADCCFG. The time between each channel pair conversions is determined by: (32000000/ADCDLY)Hz. Note that exceeding 100KHz will result in the ADC chips delaying until they are ready to complete another conversion. Once the ADC conversion state machine has sampled the NUMCHAN channel, it will loop back around and start over again at channel pair 0. Writing to any of the bits in ADCCFG (except SYSCOM) will clear the FIFO completely; the ADC conversion state machine will keep running, but the next FIFO entry read will be channel 0 with the new configuration settings. The ADC conversion state machine will run until: it is stopped by clearing SYSCOM, or if the FIFO completely fills up with 512 samples.

Samples are stored in to the FIFO in channel order. Reading ADCFIFO or ADCFIFO_MSB will consume the next sample in the FIFO. If INTEN is set, an interrupt will be triggered when the FIFO count reaches the specified FFCOUNT(WO) number. This defaults to half full, 256 samples. The PC/104 IRQ number is chosen by the jumper configuration, see Jumpers for more information.

The ADCSTAT register is a read-only/write-only/read-write register. INTEN can be read/written at any time to enable or disable interrupt triggering at FFCOUNT(WO). FFHEAD is read-only, current channel available in ADCFIFO (Note: channel, not channel pair). FFCOUNT is read-only and write-only. Reading FFCOUNT(RO) will show the current FIFO count. Writing FFCOUNT(WO) will set the FIFO count at which an interrupt gets triggered if INTEN is set.

Converting a channel value to voltage is done with the following equations:

 Unipolar: (unsigned short)((vmax/65535)*value)
 Bipolar: (signed short)((vmax-vmin)/65535)*value)

It is important to used signed numbers when in bipolar mode.

Acquisition mode

Single Ended

In single ended mode, each channel's input voltage is compared to ground. Analog ground is tied to digital ground.

Differential

In differential mode, two input pins are used for conversion. For example, V+ is connected to AD1_0, and V- is connected to AD1_1, this means that the input pins are connected to channel 0 and 2 respectively. When reading channel 0, the value of V+ with respect to V- is returned. When reading channel 2, the value of V- with respect to V+ is returned. In the case of Bipolar mode, channel 0 would read positive voltage and channel 2 would read the negative of that voltage. In unipolar mode, channel 0 would return a positive voltage and channel 2 would return 0v.

Register Map

Offset	Register Name	Bits	Access	Description
0x0	BID: Board ID register	15:12	RO	Jumper status {jp4, jp3, jp2, jp1}
		11:8	RO	PLD Revision (0x5 is latest)
		7:0	RO	Board ID = 0x3e
0x2	ADCCFG ADC Config. register Writing to bits 1-8 of this register causes the system to reset	15:9	RO	Reserved
		8	RW	Global single ended/differential (OR'ed with bit 5) 1 = single ended 0 = differential
		7:6	RW	Global analog input range 00 = -5v to +5v 01 = 0v to +5v 10 = -10v to +10v 11 = 0v to +10v
		5	RW	Global single ended/differential (OR'ed with bit 8) 1 = single ended 0 = differential
		4:1	RW	NUMCHAN Max channel pair number to sample in full cycle See ADC pins
		0	RW	SYSCOM 0 = stop system/system stopped 1 = start system/system running
0x4	ADCDLY_MSB	15:8	RO	Reserved
		7:0	RW	Bits 23:16 of 24-bit pacing clock counter (32MHz clock)
0x6	ADCDLY_LSB	15:0	RW	Bits 15:0 of 24-bit pacing clock counter (32MHz clock)
0x8	ADCSTAT	15:6	RO	FFCOUNT(RO) Current FIFO count
			WO	FFCOUNT(WO) Set count level to trigger interrupt Default half full, 256 samples
		5:1	RO	FFHEAD Channel on the head of the FIFO
		0	RW	INTEN 0 = disable interrupt generation 1 = enable interrupt at FFCOUNT(RO) >= FFCOUNT(WO)
0xA	ADCFIFO	15:0	RO	16-bit ADC read data
0xC	Reserved	15:0	RO	Reserved
0xE	DACCMD	15:14	RW	DAC channel number
		13	RW	0 = 0v to +2.5v output 1 = 0v to +5v output
		12	RW	Write as 1
		11:0	RW	12-bit DAC output for selected channel
0x10	COUNT0	15:0	RO	Counter 0 value
0x12	COUNT1	15:0	RO	Counter 1 value
0x14	COUNT2	15:0	RO	Counter 2 value
0x16	COUNT3	15:0	RO	Counter 3 value
0x18	DIGIO	15:5	RO	Reserved
		4	RW	Output 0 data
		3	RO	Input 3 data
		2	RO	Input 2 data
		1	RO	Input 1 data
		0	RO	Input 0 data
0x1A	ADCFIFO_LSB (8-bit)	7:0	RO	8-bit ADC LSB read data
0x1B	ADCFIFO_MSB (8-bit)	7:0	RO	8-bit ADC MSF read data (consumes sample)

Connectors

Note: All even pins on ADX pin headers are grounds

ADC pins

ADC Channel	ADX_Y num.	ADX pin header	Channel pair
ADC ch.0	AD1_0	AD1 pin 1	0
ADC ch.1	AD2_0	AD2 pin 1
ADC ch.2	AD1_1	AD1 pin 3	1
ADC ch.3	AD2_1	AD2 pin 3
ADC ch.4	AD1_2	AD1 pin 5	2
ADC ch.5	AD2_2	AD2 pin 5
ADC ch.6	AD1_3	AD1 pin 7	3
ADC ch.7	AD2_3	AD2 pin 7
ADC ch.8	AD1_4	AD1 pin 9	4
ADC ch.9	AD2_4	AD2 pin 9
ADC ch.10	AD1_5	AD1 pin 11	5
ADC ch.11	AD2_5	AD2 pin 11
ADC ch.12	AD1_6	AD1 pin 13	6
ADC ch.13	N/A	AD2 pin 13
ADC ch.14	AD1_7	AD1 pin 15	7
ADC ch.15	N/A	AD2 pin 15

DAC pins

DAC channel	DACX num.	ADX pin header
DAC ch.0	DAC A	AD2 pin 19
DAC ch.1	DAC B	AD2 pin 21
DAC ch.2	DAC C	AD2 pin 23
DAC ch.3	DAC D	AD2 pin 25

Digital Input pins

Input num.	ADX pin header
Input 0	AD1 pin 19
Input 1	AD1 pin 21
Input 2	AD1 pin 23
Input 3	AD1 pin 25

Digital Output pin

Output num.	ADX pin header
Output 0	AD1 pin 17

Jumpers

PC/104 base address

JP2	JP1	Addr
Off	Off	0x100
Off	On	0x120
On	Off	0x140
On	On	0x160

ARM/x86 mode

JP3	PC/104 Mode
Off	8bit (x86)
On	TS ARM 16bit pinout

IRQ select

IRQ output is active high, sharable with other PC/104 devices, and will remain asserted as long as INTEN is set and the FIFO count is greater than FFCOUNT(WO)

JP4	IRQ
Off	IRQ6
On	IRQ7